[PATCH] D92228: [RISCV] Add MIR tests exposing missed InstAliases

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck created this revision.
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The InstAlias framework cannot match registers against zero_reg, which
RVV uses to encode unmasked operations.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D92228

Files:
  llvm/test/CodeGen/MIR/RISCV/aliases-v.mir
  llvm/test/CodeGen/MIR/RISCV/lit.local.cfg


Index: llvm/test/CodeGen/MIR/RISCV/lit.local.cfg
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/MIR/RISCV/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'RISCV' in config.root.targets:
+    config.unsupported = True
Index: llvm/test/CodeGen/MIR/RISCV/aliases-v.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/MIR/RISCV/aliases-v.mir
@@ -0,0 +1,59 @@
+# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+# RUN: llc -mtriple riscv32 -mattr=+experimental-v -start-after riscv-expand-pseudo -o - %s | FileCheck %s
+# RUN: llc -mtriple riscv64 -mattr=+experimental-v -start-after riscv-expand-pseudo -o - %s | FileCheck %s
+# FIXME: These should all use the 'vnot' alias despite not having masks
+--- |
+
+  define void @vnot_mask_1() {
+  ; CHECK-LABEL: vnot_mask_1:
+  ; CHECK:       # %bb.0:
+  ; CHECK-NEXT:    vnot.v v25, v25, v0.t
+    ret void
+  }
+  define void @vnot_mask_2() {
+  ; CHECK-LABEL: vnot_mask_2:
+  ; CHECK:       # %bb.0:
+  ; CHECK-NEXT:    vnot.v v1, v25, v0.t
+    ret void
+  }
+  define void @vnot_no_mask_1() {
+  ; CHECK-LABEL: vnot_no_mask_1:
+  ; CHECK:       # %bb.0:
+  ; CHECK-NEXT:    vxor.vi v25, v25, -1
+    ret void
+  }
+  define void @vnot_no_mask_2() {
+  ; CHECK-LABEL: vnot_no_mask_2:
+  ; CHECK:       # %bb.0:
+  ; CHECK-NEXT:    vxor.vi v1, v25, -1
+    ret void
+  }
+...
+---
+name:            vnot_mask_1
+body:             |
+  bb.0:
+    liveins: $v0, $v25
+    $v25 = VXOR_VI killed $v25, -1, $v0, implicit $vtype, implicit $vl
+...
+---
+name:            vnot_mask_2
+body:             |
+  bb.0:
+    liveins: $v0, $v25
+    $v1 = VXOR_VI killed $v25, -1, $v0, implicit $vtype, implicit $vl
+...
+---
+name:            vnot_no_mask_1
+body:             |
+  bb.0:
+    liveins: $v0, $v25
+    $v25 = VXOR_VI killed $v25, -1, $noreg, implicit $vtype, implicit $vl
+...
+---
+name:            vnot_no_mask_2
+body:             |
+  bb.0:
+    liveins: $v0, $v25
+    $v1 = VXOR_VI killed $v25, -1, $noreg, implicit $vtype, implicit $vl
+...


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