[llvm] 60c28a5 - [NFC][Test] Format the test for IEEE Long double
QingShan Zhang via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 24 19:00:50 PST 2020
Author: QingShan Zhang
Date: 2020-11-25T03:00:24Z
New Revision: 60c28a5a2b76ebf9c8bac9ebf20ac8fe69c788ee
URL: https://github.com/llvm/llvm-project/commit/60c28a5a2b76ebf9c8bac9ebf20ac8fe69c788ee
DIFF: https://github.com/llvm/llvm-project/commit/60c28a5a2b76ebf9c8bac9ebf20ac8fe69c788ee.diff
LOG: [NFC][Test] Format the test for IEEE Long double
Added:
Modified:
llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll
llvm/test/CodeGen/PowerPC/store_fptoi.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll b/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll
index ffc626be2dea..26832efb3f4c 100644
--- a/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll
@@ -1,65 +1,197 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mcpu=a2 < %s | FileCheck %s -check-prefix=FPCVT
; RUN: llc -verify-machineinstrs -mcpu=ppc64 < %s | FileCheck %s -check-prefix=PPC64
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 < %s | FileCheck %s -check-prefix=PWR9
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind readnone
define float @fool(float %X) #0 {
+; FPCVT-LABEL: fool:
+; FPCVT: # %bb.0: # %entry
+; FPCVT-NEXT: friz 1, 1
+; FPCVT-NEXT: blr
+;
+; PPC64-LABEL: fool:
+; PPC64: # %bb.0: # %entry
+; PPC64-NEXT: fctidz 0, 1
+; PPC64-NEXT: fcfid 0, 0
+; PPC64-NEXT: frsp 1, 0
+; PPC64-NEXT: blr
+;
+; PWR9-LABEL: fool:
+; PWR9: # %bb.0: # %entry
+; PWR9-NEXT: xsrdpiz 1, 1
+; PWR9-NEXT: blr
entry:
%conv = fptosi float %X to i64
%conv1 = sitofp i64 %conv to float
ret float %conv1
-; FPCVT-LABEL: @fool
-; FPCVT: friz 1, 1
-; FPCVT: blr
-; PPC64-LABEL: @fool
-; PPC64: fctidz [[REG1:[0-9]+]], 1
-; PPC64: fcfid [[REG2:[0-9]+]], [[REG1]]
-; PPC64: frsp 1, [[REG2]]
-; PPC64: blr
}
; Function Attrs: nounwind readnone
define double @foodl(double %X) #0 {
+; FPCVT-LABEL: foodl:
+; FPCVT: # %bb.0: # %entry
+; FPCVT-NEXT: friz 1, 1
+; FPCVT-NEXT: blr
+;
+; PPC64-LABEL: foodl:
+; PPC64: # %bb.0: # %entry
+; PPC64-NEXT: fctidz 0, 1
+; PPC64-NEXT: fcfid 1, 0
+; PPC64-NEXT: blr
+;
+; PWR9-LABEL: foodl:
+; PWR9: # %bb.0: # %entry
+; PWR9-NEXT: xsrdpiz 1, 1
+; PWR9-NEXT: blr
entry:
%conv = fptosi double %X to i64
%conv1 = sitofp i64 %conv to double
ret double %conv1
-; FPCVT-LABEL: @foodl
-; FPCVT: friz 1, 1
-; FPCVT: blr
-; PPC64-LABEL: @foodl
-; PPC64: fctidz [[REG1:[0-9]+]], 1
-; PPC64: fcfid 1, [[REG1]]
-; PPC64: blr
}
; Function Attrs: nounwind readnone
define float @fooul(float %X) #0 {
+; FPCVT-LABEL: fooul:
+; FPCVT: # %bb.0: # %entry
+; FPCVT-NEXT: friz 1, 1
+; FPCVT-NEXT: blr
+;
+; PPC64-LABEL: fooul:
+; PPC64: # %bb.0: # %entry
+; PPC64-NEXT: addis 3, 2, .LCPI2_0 at toc@ha
+; PPC64-NEXT: li 4, 1
+; PPC64-NEXT: lfs 0, .LCPI2_0 at toc@l(3)
+; PPC64-NEXT: sldi 4, 4, 63
+; PPC64-NEXT: fsubs 2, 1, 0
+; PPC64-NEXT: fcmpu 0, 1, 0
+; PPC64-NEXT: fctidz 2, 2
+; PPC64-NEXT: stfd 2, -8(1)
+; PPC64-NEXT: fctidz 2, 1
+; PPC64-NEXT: stfd 2, -16(1)
+; PPC64-NEXT: ld 3, -8(1)
+; PPC64-NEXT: ld 5, -16(1)
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: bc 12, 0, .LBB2_1
+; PPC64-NEXT: b .LBB2_2
+; PPC64-NEXT: .LBB2_1: # %entry
+; PPC64-NEXT: addi 3, 5, 0
+; PPC64-NEXT: .LBB2_2: # %entry
+; PPC64-NEXT: sradi 4, 3, 53
+; PPC64-NEXT: clrldi 5, 3, 63
+; PPC64-NEXT: addi 4, 4, 1
+; PPC64-NEXT: cmpldi 4, 1
+; PPC64-NEXT: rldicl 4, 3, 63, 1
+; PPC64-NEXT: or 5, 5, 4
+; PPC64-NEXT: rldicl 6, 5, 11, 53
+; PPC64-NEXT: addi 6, 6, 1
+; PPC64-NEXT: clrldi 7, 5, 53
+; PPC64-NEXT: cmpldi 1, 6, 1
+; PPC64-NEXT: clrldi 6, 3, 53
+; PPC64-NEXT: addi 7, 7, 2047
+; PPC64-NEXT: addi 6, 6, 2047
+; PPC64-NEXT: or 4, 7, 4
+; PPC64-NEXT: or 6, 6, 3
+; PPC64-NEXT: rldicl 4, 4, 53, 11
+; PPC64-NEXT: rldicr 6, 6, 0, 52
+; PPC64-NEXT: bc 12, 1, .LBB2_4
+; PPC64-NEXT: # %bb.3: # %entry
+; PPC64-NEXT: ori 6, 3, 0
+; PPC64-NEXT: b .LBB2_4
+; PPC64-NEXT: .LBB2_4: # %entry
+; PPC64-NEXT: rldicl 4, 4, 11, 1
+; PPC64-NEXT: cmpdi 3, 0
+; PPC64-NEXT: std 6, -32(1)
+; PPC64-NEXT: bc 12, 5, .LBB2_6
+; PPC64-NEXT: # %bb.5: # %entry
+; PPC64-NEXT: ori 4, 5, 0
+; PPC64-NEXT: b .LBB2_6
+; PPC64-NEXT: .LBB2_6: # %entry
+; PPC64-NEXT: std 4, -24(1)
+; PPC64-NEXT: bc 12, 0, .LBB2_8
+; PPC64-NEXT: # %bb.7: # %entry
+; PPC64-NEXT: lfd 0, -32(1)
+; PPC64-NEXT: fcfid 0, 0
+; PPC64-NEXT: frsp 1, 0
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB2_8:
+; PPC64-NEXT: lfd 0, -24(1)
+; PPC64-NEXT: fcfid 0, 0
+; PPC64-NEXT: frsp 0, 0
+; PPC64-NEXT: fadds 1, 0, 0
+; PPC64-NEXT: blr
+;
+; PWR9-LABEL: fooul:
+; PWR9: # %bb.0: # %entry
+; PWR9-NEXT: xsrdpiz 1, 1
+; PWR9-NEXT: blr
entry:
%conv = fptoui float %X to i64
%conv1 = uitofp i64 %conv to float
ret float %conv1
-; FPCVT-LABEL: @fooul
-; FPCVT: friz 1, 1
-; FPCVT: blr
}
; Function Attrs: nounwind readnone
define double @fooudl(double %X) #0 {
+; FPCVT-LABEL: fooudl:
+; FPCVT: # %bb.0: # %entry
+; FPCVT-NEXT: friz 1, 1
+; FPCVT-NEXT: blr
+;
+; PPC64-LABEL: fooudl:
+; PPC64: # %bb.0: # %entry
+; PPC64-NEXT: addis 3, 2, .LCPI3_0 at toc@ha
+; PPC64-NEXT: li 4, 1
+; PPC64-NEXT: lfs 0, .LCPI3_0 at toc@l(3)
+; PPC64-NEXT: sldi 4, 4, 63
+; PPC64-NEXT: fsub 2, 1, 0
+; PPC64-NEXT: fcmpu 0, 1, 0
+; PPC64-NEXT: fctidz 2, 2
+; PPC64-NEXT: stfd 2, -8(1)
+; PPC64-NEXT: fctidz 2, 1
+; PPC64-NEXT: stfd 2, -16(1)
+; PPC64-NEXT: ld 3, -8(1)
+; PPC64-NEXT: ld 5, -16(1)
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: li 4, 1107
+; PPC64-NEXT: sldi 4, 4, 52
+; PPC64-NEXT: bc 12, 0, .LBB3_1
+; PPC64-NEXT: b .LBB3_2
+; PPC64-NEXT: .LBB3_1: # %entry
+; PPC64-NEXT: addi 3, 5, 0
+; PPC64-NEXT: .LBB3_2: # %entry
+; PPC64-NEXT: rldicl 5, 3, 32, 32
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: or 4, 5, 4
+; PPC64-NEXT: addis 5, 2, .LCPI3_1 at toc@ha
+; PPC64-NEXT: std 4, -24(1)
+; PPC64-NEXT: li 4, 1075
+; PPC64-NEXT: sldi 4, 4, 52
+; PPC64-NEXT: or 3, 3, 4
+; PPC64-NEXT: lfd 0, .LCPI3_1 at toc@l(5)
+; PPC64-NEXT: std 3, -32(1)
+; PPC64-NEXT: lfd 1, -24(1)
+; PPC64-NEXT: lfd 2, -32(1)
+; PPC64-NEXT: fsub 0, 1, 0
+; PPC64-NEXT: fadd 1, 2, 0
+; PPC64-NEXT: blr
+;
+; PWR9-LABEL: fooudl:
+; PWR9: # %bb.0: # %entry
+; PWR9-NEXT: xsrdpiz 1, 1
+; PWR9-NEXT: blr
entry:
%conv = fptoui double %X to i64
%conv1 = uitofp i64 %conv to double
ret double %conv1
-; FPCVT-LABEL: @fooudl
-; FPCVT: friz 1, 1
-; FPCVT: blr
}
attributes #0 = { nounwind readnone "no-signed-zeros-fp-math"="true" }
diff --git a/llvm/test/CodeGen/PowerPC/store_fptoi.ll b/llvm/test/CodeGen/PowerPC/store_fptoi.ll
index 1e5b8414243b..737ead9946f1 100644
--- a/llvm/test/CodeGen/PowerPC/store_fptoi.ll
+++ b/llvm/test/CodeGen/PowerPC/store_fptoi.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \
; RUN: -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \
@@ -9,254 +10,377 @@
; Function Attrs: norecurse nounwind
define void @qpConv2sdw(fp128* nocapture readonly %a, i64* nocapture %b) {
+; CHECK-LABEL: qpConv2sdw:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lxv 2, 0(3)
+; CHECK-NEXT: xscvqpsdz 2, 2
+; CHECK-NEXT: stxsd 2, 0(4)
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: qpConv2sdw:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: mflr 0
+; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 48
+; CHECK-PWR8-NEXT: .cfi_offset lr, 16
+; CHECK-PWR8-NEXT: .cfi_offset r30, -16
+; CHECK-PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill
+; CHECK-PWR8-NEXT: std 0, 16(1)
+; CHECK-PWR8-NEXT: stdu 1, -48(1)
+; CHECK-PWR8-NEXT: ld 5, 0(3)
+; CHECK-PWR8-NEXT: ld 6, 8(3)
+; CHECK-PWR8-NEXT: mr 30, 4
+; CHECK-PWR8-NEXT: mr 3, 5
+; CHECK-PWR8-NEXT: mr 4, 6
+; CHECK-PWR8-NEXT: bl __fixkfdi
+; CHECK-PWR8-NEXT: nop
+; CHECK-PWR8-NEXT: std 3, 0(30)
+; CHECK-PWR8-NEXT: addi 1, 1, 48
+; CHECK-PWR8-NEXT: ld 0, 16(1)
+; CHECK-PWR8-NEXT: ld 30, -16(1) # 8-byte Folded Reload
+; CHECK-PWR8-NEXT: mtlr 0
+; CHECK-PWR8-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
%conv = fptosi fp128 %0 to i64
store i64 %conv, i64* %b, align 8
ret void
-; CHECK-LABEL: qpConv2sdw
-; CHECK: lxv [[LD:[0-9]+]], 0(3)
-; CHECK-NEXT: xscvqpsdz [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stxsd [[CONV]], 0(4)
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: qpConv2sdw
-; CHECK-PWR8: bl __fixkfdi
-; CHECK-PWR8: blr
}
; Function Attrs: norecurse nounwind
define void @qpConv2sw(fp128* nocapture readonly %a, i32* nocapture %b) {
+; CHECK-LABEL: qpConv2sw:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lxv 2, 0(3)
+; CHECK-NEXT: xscvqpswz 2, 2
+; CHECK-NEXT: stxsiwx 2, 0, 4
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: qpConv2sw:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: mflr 0
+; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 48
+; CHECK-PWR8-NEXT: .cfi_offset lr, 16
+; CHECK-PWR8-NEXT: .cfi_offset r30, -16
+; CHECK-PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill
+; CHECK-PWR8-NEXT: std 0, 16(1)
+; CHECK-PWR8-NEXT: stdu 1, -48(1)
+; CHECK-PWR8-NEXT: ld 5, 0(3)
+; CHECK-PWR8-NEXT: ld 6, 8(3)
+; CHECK-PWR8-NEXT: mr 30, 4
+; CHECK-PWR8-NEXT: mr 3, 5
+; CHECK-PWR8-NEXT: mr 4, 6
+; CHECK-PWR8-NEXT: bl __fixkfsi
+; CHECK-PWR8-NEXT: nop
+; CHECK-PWR8-NEXT: stw 3, 0(30)
+; CHECK-PWR8-NEXT: addi 1, 1, 48
+; CHECK-PWR8-NEXT: ld 0, 16(1)
+; CHECK-PWR8-NEXT: ld 30, -16(1) # 8-byte Folded Reload
+; CHECK-PWR8-NEXT: mtlr 0
+; CHECK-PWR8-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
%conv = fptosi fp128 %0 to i32
store i32 %conv, i32* %b, align 4
ret void
-; CHECK-LABEL: qpConv2sw
-; CHECK: lxv [[LD:[0-9]+]], 0(3)
-; CHECK-NEXT: xscvqpswz [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stxsiwx [[CONV]], 0, 4
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: qpConv2sw
-; CHECK-PWR8: bl __fixkfsi
-; CHECK-PWR8: blr
}
; Function Attrs: norecurse nounwind
define void @qpConv2udw(fp128* nocapture readonly %a, i64* nocapture %b) {
+; CHECK-LABEL: qpConv2udw:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lxv 2, 0(3)
+; CHECK-NEXT: xscvqpudz 2, 2
+; CHECK-NEXT: stxsd 2, 0(4)
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: qpConv2udw:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: mflr 0
+; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 48
+; CHECK-PWR8-NEXT: .cfi_offset lr, 16
+; CHECK-PWR8-NEXT: .cfi_offset r30, -16
+; CHECK-PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill
+; CHECK-PWR8-NEXT: std 0, 16(1)
+; CHECK-PWR8-NEXT: stdu 1, -48(1)
+; CHECK-PWR8-NEXT: ld 5, 0(3)
+; CHECK-PWR8-NEXT: ld 6, 8(3)
+; CHECK-PWR8-NEXT: mr 30, 4
+; CHECK-PWR8-NEXT: mr 3, 5
+; CHECK-PWR8-NEXT: mr 4, 6
+; CHECK-PWR8-NEXT: bl __fixunskfdi
+; CHECK-PWR8-NEXT: nop
+; CHECK-PWR8-NEXT: std 3, 0(30)
+; CHECK-PWR8-NEXT: addi 1, 1, 48
+; CHECK-PWR8-NEXT: ld 0, 16(1)
+; CHECK-PWR8-NEXT: ld 30, -16(1) # 8-byte Folded Reload
+; CHECK-PWR8-NEXT: mtlr 0
+; CHECK-PWR8-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
%conv = fptoui fp128 %0 to i64
store i64 %conv, i64* %b, align 8
ret void
-; CHECK-LABEL: qpConv2udw
-; CHECK: lxv [[LD:[0-9]+]], 0(3)
-; CHECK-NEXT: xscvqpudz [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stxsd [[CONV]], 0(4)
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: qpConv2udw
-; CHECK-PWR8: bl __fixunskfdi
-; CHECK-PWR8: blr
}
; Function Attrs: norecurse nounwind
define void @qpConv2uw(fp128* nocapture readonly %a, i32* nocapture %b) {
+; CHECK-LABEL: qpConv2uw:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lxv 2, 0(3)
+; CHECK-NEXT: xscvqpuwz 2, 2
+; CHECK-NEXT: stxsiwx 2, 0, 4
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: qpConv2uw:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: mflr 0
+; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 48
+; CHECK-PWR8-NEXT: .cfi_offset lr, 16
+; CHECK-PWR8-NEXT: .cfi_offset r30, -16
+; CHECK-PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill
+; CHECK-PWR8-NEXT: std 0, 16(1)
+; CHECK-PWR8-NEXT: stdu 1, -48(1)
+; CHECK-PWR8-NEXT: ld 5, 0(3)
+; CHECK-PWR8-NEXT: ld 6, 8(3)
+; CHECK-PWR8-NEXT: mr 30, 4
+; CHECK-PWR8-NEXT: mr 3, 5
+; CHECK-PWR8-NEXT: mr 4, 6
+; CHECK-PWR8-NEXT: bl __fixunskfsi
+; CHECK-PWR8-NEXT: nop
+; CHECK-PWR8-NEXT: stw 3, 0(30)
+; CHECK-PWR8-NEXT: addi 1, 1, 48
+; CHECK-PWR8-NEXT: ld 0, 16(1)
+; CHECK-PWR8-NEXT: ld 30, -16(1) # 8-byte Folded Reload
+; CHECK-PWR8-NEXT: mtlr 0
+; CHECK-PWR8-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
%conv = fptoui fp128 %0 to i32
store i32 %conv, i32* %b, align 4
ret void
-; CHECK-LABEL: qpConv2uw
-; CHECK: lxv [[LD:[0-9]+]], 0(3)
-; CHECK-NEXT: xscvqpuwz [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stxsiwx [[CONV]], 0, 4
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: qpConv2uw
-; CHECK-PWR8: bl __fixunskfsi
-; CHECK-PWR8: blr
}
; Function Attrs: norecurse nounwind
define void @dpConv2sdw(double* nocapture readonly %a, i64* nocapture %b) {
+; CHECK-LABEL: dpConv2sdw:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfd 0, 0(3)
+; CHECK-NEXT: xscvdpsxds 2, 0
+; CHECK-NEXT: stxsd 2, 0(4)
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: dpConv2sdw:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfdx 0, 0, 3
+; CHECK-PWR8-NEXT: xscvdpsxds 0, 0
+; CHECK-PWR8-NEXT: stxsdx 0, 0, 4
+; CHECK-PWR8-NEXT: blr
entry:
%0 = load double, double* %a, align 8
%conv = fptosi double %0 to i64
store i64 %conv, i64* %b, align 8
ret void
-; CHECK-LABEL: dpConv2sdw
-; CHECK: lfd [[LD:[0-9]+]], 0(3)
-; CHECK: xscvdpsxds [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stxsd [[CONV]], 0(4)
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: dpConv2sdw
-; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: xscvdpsxds [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: stxsdx [[CONV]], 0, 4
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @dpConv2sw(double* nocapture readonly %a, i32* nocapture %b) {
+; CHECK-LABEL: dpConv2sw:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfd 0, 0(3)
+; CHECK-NEXT: xscvdpsxws 0, 0
+; CHECK-NEXT: stfiwx 0, 0, 4
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: dpConv2sw:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfdx 0, 0, 3
+; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
+; CHECK-PWR8-NEXT: stfiwx 0, 0, 4
+; CHECK-PWR8-NEXT: blr
entry:
%0 = load double, double* %a, align 8
%conv = fptosi double %0 to i32
store i32 %conv, i32* %b, align 4
ret void
-; CHECK-LABEL: dpConv2sw
-; CHECK: lfd [[LD:[0-9]+]], 0(3)
-; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stfiwx [[CONV]], 0, 4
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: dpConv2sw
-; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: stfiwx [[CONV]], 0, 4
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @dpConv2shw(double* nocapture readonly %a, i16* nocapture %b) {
+; CHECK-LABEL: dpConv2shw:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfd 0, 0(3)
+; CHECK-NEXT: xscvdpsxws 0, 0
+; CHECK-NEXT: stxsihx 0, 0, 4
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: dpConv2shw:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfdx 0, 0, 3
+; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
+; CHECK-PWR8-NEXT: mffprwz 3, 0
+; CHECK-PWR8-NEXT: sth 3, 0(4)
+; CHECK-PWR8-NEXT: blr
entry:
%0 = load double, double* %a, align 8
%conv = fptosi double %0 to i16
store i16 %conv, i16* %b, align 2
ret void
-; CHECK-LABEL: dpConv2shw
-; CHECK: lfd [[LD:[0-9]+]], 0(3)
-; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stxsihx [[CONV]], 0, 4
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: dpConv2shw
-; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
-; CHECK-PWR8-NEXT: sth [[REG]], 0(4)
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @dpConv2sb(double* nocapture readonly %a, i8* nocapture %b) {
+; CHECK-LABEL: dpConv2sb:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfd 0, 0(3)
+; CHECK-NEXT: xscvdpsxws 0, 0
+; CHECK-NEXT: stxsibx 0, 0, 4
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: dpConv2sb:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfdx 0, 0, 3
+; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
+; CHECK-PWR8-NEXT: mffprwz 3, 0
+; CHECK-PWR8-NEXT: stb 3, 0(4)
+; CHECK-PWR8-NEXT: blr
entry:
%0 = load double, double* %a, align 8
%conv = fptosi double %0 to i8
store i8 %conv, i8* %b, align 1
ret void
-; CHECK-LABEL: dpConv2sb
-; CHECK: lfd [[LD:[0-9]+]], 0(3)
-; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stxsibx [[CONV]], 0, 4
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: dpConv2sb
-; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
-; CHECK-PWR8-NEXT: stb [[REG]], 0(4)
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @spConv2sdw(float* nocapture readonly %a, i64* nocapture %b) {
+; CHECK-LABEL: spConv2sdw:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfs 0, 0(3)
+; CHECK-NEXT: xscvdpsxds 2, 0
+; CHECK-NEXT: stxsd 2, 0(4)
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: spConv2sdw:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfsx 0, 0, 3
+; CHECK-PWR8-NEXT: xscvdpsxds 0, 0
+; CHECK-PWR8-NEXT: stxsdx 0, 0, 4
+; CHECK-PWR8-NEXT: blr
entry:
%0 = load float, float* %a, align 4
%conv = fptosi float %0 to i64
store i64 %conv, i64* %b, align 8
ret void
-; CHECK-LABEL: spConv2sdw
-; CHECK: lfs [[LD:[0-9]+]], 0(3)
-; CHECK-NEXT: xscvdpsxds [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stxsd [[CONV]], 0(4)
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: spConv2sdw
-; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: xscvdpsxds [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: stxsdx [[CONV]], 0, 4
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @spConv2sw(float* nocapture readonly %a, i32* nocapture %b) {
+; CHECK-LABEL: spConv2sw:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfs 0, 0(3)
+; CHECK-NEXT: xscvdpsxws 0, 0
+; CHECK-NEXT: stfiwx 0, 0, 4
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: spConv2sw:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfsx 0, 0, 3
+; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
+; CHECK-PWR8-NEXT: stfiwx 0, 0, 4
+; CHECK-PWR8-NEXT: blr
entry:
%0 = load float, float* %a, align 4
%conv = fptosi float %0 to i32
store i32 %conv, i32* %b, align 4
ret void
-; CHECK-LABEL: spConv2sw
-; CHECK: lfs [[LD:[0-9]+]], 0(3)
-; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stfiwx [[CONV]], 0, 4
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: spConv2sw
-; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: stfiwx [[CONV]], 0, 4
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @spConv2shw(float* nocapture readonly %a, i16* nocapture %b) {
+; CHECK-LABEL: spConv2shw:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfs 0, 0(3)
+; CHECK-NEXT: xscvdpsxws 0, 0
+; CHECK-NEXT: stxsihx 0, 0, 4
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: spConv2shw:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfsx 0, 0, 3
+; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
+; CHECK-PWR8-NEXT: mffprwz 3, 0
+; CHECK-PWR8-NEXT: sth 3, 0(4)
+; CHECK-PWR8-NEXT: blr
entry:
%0 = load float, float* %a, align 4
%conv = fptosi float %0 to i16
store i16 %conv, i16* %b, align 2
ret void
-; CHECK-LABEL: spConv2shw
-; CHECK: lfs [[LD:[0-9]+]], 0(3)
-; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stxsihx [[CONV]], 0, 4
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: spConv2shw
-; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
-; CHECK-PWR8-NEXT: sth [[REG]], 0(4)
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @spConv2sb(float* nocapture readonly %a, i8* nocapture %b) {
+; CHECK-LABEL: spConv2sb:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfs 0, 0(3)
+; CHECK-NEXT: xscvdpsxws 0, 0
+; CHECK-NEXT: stxsibx 0, 0, 4
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: spConv2sb:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfsx 0, 0, 3
+; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
+; CHECK-PWR8-NEXT: mffprwz 3, 0
+; CHECK-PWR8-NEXT: stb 3, 0(4)
+; CHECK-PWR8-NEXT: blr
entry:
%0 = load float, float* %a, align 4
%conv = fptosi float %0 to i8
store i8 %conv, i8* %b, align 1
ret void
-; CHECK-LABEL: spConv2sb
-; CHECK: lfs [[LD:[0-9]+]], 0(3)
-; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stxsibx [[CONV]], 0, 4
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: spConv2sb
-; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
-; CHECK-PWR8-NEXT: stb [[REG]], 0(4)
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @dpConv2sdw_x(double* nocapture readonly %a, i64* nocapture %b,
+; CHECK-LABEL: dpConv2sdw_x:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfd 0, 0(3)
+; CHECK-NEXT: sldi 3, 5, 3
+; CHECK-NEXT: xscvdpsxds 0, 0
+; CHECK-NEXT: stxsdx 0, 4, 3
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: dpConv2sdw_x:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfdx 0, 0, 3
+; CHECK-PWR8-NEXT: sldi 3, 5, 3
+; CHECK-PWR8-NEXT: xscvdpsxds 0, 0
+; CHECK-PWR8-NEXT: stxsdx 0, 4, 3
+; CHECK-PWR8-NEXT: blr
i32 signext %idx) {
entry:
%0 = load double, double* %a, align 8
@@ -266,23 +390,26 @@ entry:
store i64 %conv, i64* %arrayidx, align 8
ret void
-; CHECK-LABEL: dpConv2sdw_x
-; CHECK: lfd [[LD:[0-9]+]], 0(3)
-; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 3
-; CHECK-NEXT: xscvdpsxds [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stxsdx [[CONV]], 4, [[REG]]
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: dpConv2sdw_x
-; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8: sldi [[REG:[0-9]+]], 5, 3
-; CHECK-PWR8-NEXT: xscvdpsxds [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: stxsdx [[CONV]], 4, [[REG]]
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @dpConv2sw_x(double* nocapture readonly %a, i32* nocapture %b,
+; CHECK-LABEL: dpConv2sw_x:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfd 0, 0(3)
+; CHECK-NEXT: sldi 3, 5, 2
+; CHECK-NEXT: xscvdpsxws 0, 0
+; CHECK-NEXT: stfiwx 0, 4, 3
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: dpConv2sw_x:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfdx 0, 0, 3
+; CHECK-PWR8-NEXT: sldi 3, 5, 2
+; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
+; CHECK-PWR8-NEXT: stfiwx 0, 4, 3
+; CHECK-PWR8-NEXT: blr
i32 signext %idx) {
entry:
%0 = load double, double* %a, align 8
@@ -292,23 +419,27 @@ entry:
store i32 %conv, i32* %arrayidx, align 4
ret void
-; CHECK-LABEL: dpConv2sw_x
-; CHECK: lfd [[LD:[0-9]+]], 0(3)
-; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 2
-; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stfiwx [[CONV]], 4, [[REG]]
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: dpConv2sw_x
-; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 2
-; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: stfiwx [[CONV]], 4, [[REG]]
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @dpConv2shw_x(double* nocapture readonly %a, i16* nocapture %b,
+; CHECK-LABEL: dpConv2shw_x:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfd 0, 0(3)
+; CHECK-NEXT: sldi 3, 5, 1
+; CHECK-NEXT: xscvdpsxws 0, 0
+; CHECK-NEXT: stxsihx 0, 4, 3
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: dpConv2shw_x:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfdx 0, 0, 3
+; CHECK-PWR8-NEXT: sldi 5, 5, 1
+; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
+; CHECK-PWR8-NEXT: mffprwz 3, 0
+; CHECK-PWR8-NEXT: sthx 3, 4, 5
+; CHECK-PWR8-NEXT: blr
i32 signext %idx) {
entry:
%0 = load double, double* %a, align 8
@@ -318,24 +449,25 @@ entry:
store i16 %conv, i16* %arrayidx, align 2
ret void
-; CHECK-LABEL: dpConv2shw_x
-; CHECK: lfd [[LD:[0-9]+]], 0(3)
-; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 1
-; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stxsihx [[CONV]], 4, [[REG]]
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: dpConv2shw_x
-; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1
-; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
-; CHECK-PWR8-NEXT: sthx [[REG]], 4, 5
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @dpConv2sb_x(double* nocapture readonly %a, i8* nocapture %b,
+; CHECK-LABEL: dpConv2sb_x:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfd 0, 0(3)
+; CHECK-NEXT: xscvdpsxws 0, 0
+; CHECK-NEXT: stxsibx 0, 4, 5
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: dpConv2sb_x:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfdx 0, 0, 3
+; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
+; CHECK-PWR8-NEXT: mffprwz 3, 0
+; CHECK-PWR8-NEXT: stbx 3, 4, 5
+; CHECK-PWR8-NEXT: blr
i32 signext %idx) {
entry:
%0 = load double, double* %a, align 8
@@ -345,22 +477,26 @@ entry:
store i8 %conv, i8* %arrayidx, align 1
ret void
-; CHECK-LABEL: dpConv2sb_x
-; CHECK: lfd [[LD:[0-9]+]], 0(3)
-; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stxsibx [[CONV]], 4, 5
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: dpConv2sb_x
-; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
-; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @spConv2sdw_x(float* nocapture readonly %a, i64* nocapture %b,
+; CHECK-LABEL: spConv2sdw_x:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfs 0, 0(3)
+; CHECK-NEXT: xscvdpsxds 0, 0
+; CHECK-NEXT: sldi 5, 5, 3
+; CHECK-NEXT: stxsdx 0, 4, 5
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: spConv2sdw_x:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfsx 0, 0, 3
+; CHECK-PWR8-NEXT: sldi 3, 5, 3
+; CHECK-PWR8-NEXT: xscvdpsxds 0, 0
+; CHECK-PWR8-NEXT: stxsdx 0, 4, 3
+; CHECK-PWR8-NEXT: blr
i32 signext %idx) {
entry:
%0 = load float, float* %a, align 4
@@ -370,23 +506,26 @@ entry:
store i64 %conv, i64* %arrayidx, align 8
ret void
-; CHECK-LABEL: spConv2sdw_x
-; CHECK: lfs [[LD:[0-9]+]], 0(3)
-; CHECK-DAG: sldi [[REG:[0-9]+]], 5, 3
-; CHECK-DAG: xscvdpsxds [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stxsdx [[CONV]], 4, [[REG]]
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: spConv2sdw_x
-; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 3
-; CHECK-PWR8-NEXT: xscvdpsxds [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: stxsdx [[CONV]], 4, [[REG]]
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @spConv2sw_x(float* nocapture readonly %a, i32* nocapture %b,
+; CHECK-LABEL: spConv2sw_x:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfs 0, 0(3)
+; CHECK-NEXT: xscvdpsxws 0, 0
+; CHECK-NEXT: sldi 5, 5, 2
+; CHECK-NEXT: stfiwx 0, 4, 5
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: spConv2sw_x:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfsx 0, 0, 3
+; CHECK-PWR8-NEXT: sldi 3, 5, 2
+; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
+; CHECK-PWR8-NEXT: stfiwx 0, 4, 3
+; CHECK-PWR8-NEXT: blr
i32 signext %idx) {
entry:
%0 = load float, float* %a, align 4
@@ -396,23 +535,27 @@ entry:
store i32 %conv, i32* %arrayidx, align 4
ret void
-; CHECK-LABEL: spConv2sw_x
-; CHECK: lfs [[LD:[0-9]+]], 0(3)
-; CHECK-DAG: sldi [[REG:[0-9]+]], 5, 2
-; CHECK-DAG: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stfiwx [[CONV]], 4, [[REG]]
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: spConv2sw_x
-; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 2
-; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: stfiwx [[CONV]], 4, [[REG]]
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @spConv2shw_x(float* nocapture readonly %a, i16* nocapture %b,
+; CHECK-LABEL: spConv2shw_x:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfs 0, 0(3)
+; CHECK-NEXT: xscvdpsxws 0, 0
+; CHECK-NEXT: sldi 5, 5, 1
+; CHECK-NEXT: stxsihx 0, 4, 5
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: spConv2shw_x:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfsx 0, 0, 3
+; CHECK-PWR8-NEXT: sldi 5, 5, 1
+; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
+; CHECK-PWR8-NEXT: mffprwz 3, 0
+; CHECK-PWR8-NEXT: sthx 3, 4, 5
+; CHECK-PWR8-NEXT: blr
i32 signext %idx) {
entry:
%0 = load float, float* %a, align 4
@@ -422,24 +565,25 @@ entry:
store i16 %conv, i16* %arrayidx, align 2
ret void
-; CHECK-LABEL: spConv2shw_x
-; CHECK: lfs [[LD:[0-9]+]], 0(3)
-; CHECK-DAG: sldi [[REG:[0-9]+]], 5, 1
-; CHECK-DAG: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stxsihx [[CONV]], 4, [[REG]]
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: spConv2shw_x
-; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1
-; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mffprwz [[REG2:[0-9]+]], [[CONV]]
-; CHECK-PWR8-NEXT: sthx [[REG2]], 4, [[REG]]
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @spConv2sb_x(float* nocapture readonly %a, i8* nocapture %b,
+; CHECK-LABEL: spConv2sb_x:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfs 0, 0(3)
+; CHECK-NEXT: xscvdpsxws 0, 0
+; CHECK-NEXT: stxsibx 0, 4, 5
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: spConv2sb_x:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfsx 0, 0, 3
+; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
+; CHECK-PWR8-NEXT: mffprwz 3, 0
+; CHECK-PWR8-NEXT: stbx 3, 4, 5
+; CHECK-PWR8-NEXT: blr
i32 signext %idx) {
entry:
%0 = load float, float* %a, align 4
@@ -449,18 +593,7 @@ entry:
store i8 %conv, i8* %arrayidx, align 1
ret void
-; CHECK-LABEL: spConv2sb_x
-; CHECK: lfs [[LD:[0-9]+]], 0(3)
-; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stxsibx [[CONV]], 4, 5
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: spConv2sb_x
-; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
-; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5
-; CHECK-PWR8-NEXT: blr
}
; ==========================================
@@ -469,178 +602,217 @@ entry:
; Function Attrs: norecurse nounwind
define void @dpConv2udw(double* nocapture readonly %a, i64* nocapture %b) {
+; CHECK-LABEL: dpConv2udw:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfd 0, 0(3)
+; CHECK-NEXT: xscvdpuxds 2, 0
+; CHECK-NEXT: stxsd 2, 0(4)
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: dpConv2udw:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfdx 0, 0, 3
+; CHECK-PWR8-NEXT: xscvdpuxds 0, 0
+; CHECK-PWR8-NEXT: stxsdx 0, 0, 4
+; CHECK-PWR8-NEXT: blr
entry:
%0 = load double, double* %a, align 8
%conv = fptoui double %0 to i64
store i64 %conv, i64* %b, align 8
ret void
-; CHECK-LABEL: dpConv2udw
-; CHECK: lfd [[LD:[0-9]+]], 0(3)
-; CHECK: xscvdpuxds [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stxsd [[CONV]], 0(4)
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: dpConv2udw
-; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: xscvdpuxds [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: stxsdx [[CONV]], 0, 4
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @dpConv2uw(double* nocapture readonly %a, i32* nocapture %b) {
+; CHECK-LABEL: dpConv2uw:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfd 0, 0(3)
+; CHECK-NEXT: xscvdpuxws 0, 0
+; CHECK-NEXT: stfiwx 0, 0, 4
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: dpConv2uw:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfdx 0, 0, 3
+; CHECK-PWR8-NEXT: xscvdpuxws 0, 0
+; CHECK-PWR8-NEXT: stfiwx 0, 0, 4
+; CHECK-PWR8-NEXT: blr
entry:
%0 = load double, double* %a, align 8
%conv = fptoui double %0 to i32
store i32 %conv, i32* %b, align 4
ret void
-; CHECK-LABEL: dpConv2uw
-; CHECK: lfd [[LD:[0-9]+]], 0(3)
-; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stfiwx [[CONV]], 0, 4
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: dpConv2uw
-; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: stfiwx [[CONV]], 0, 4
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @dpConv2uhw(double* nocapture readonly %a, i16* nocapture %b) {
+; CHECK-LABEL: dpConv2uhw:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfd 0, 0(3)
+; CHECK-NEXT: xscvdpuxws 0, 0
+; CHECK-NEXT: stxsihx 0, 0, 4
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: dpConv2uhw:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfdx 0, 0, 3
+; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
+; CHECK-PWR8-NEXT: mffprwz 3, 0
+; CHECK-PWR8-NEXT: sth 3, 0(4)
+; CHECK-PWR8-NEXT: blr
entry:
%0 = load double, double* %a, align 8
%conv = fptoui double %0 to i16
store i16 %conv, i16* %b, align 2
ret void
-; CHECK-LABEL: dpConv2uhw
-; CHECK: lfd [[LD:[0-9]+]], 0(3)
-; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stxsihx [[CONV]], 0, 4
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: dpConv2uhw
-; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
-; CHECK-PWR8-NEXT: sth [[REG]], 0(4)
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @dpConv2ub(double* nocapture readonly %a, i8* nocapture %b) {
+; CHECK-LABEL: dpConv2ub:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfd 0, 0(3)
+; CHECK-NEXT: xscvdpuxws 0, 0
+; CHECK-NEXT: stxsibx 0, 0, 4
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: dpConv2ub:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfdx 0, 0, 3
+; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
+; CHECK-PWR8-NEXT: mffprwz 3, 0
+; CHECK-PWR8-NEXT: stb 3, 0(4)
+; CHECK-PWR8-NEXT: blr
entry:
%0 = load double, double* %a, align 8
%conv = fptoui double %0 to i8
store i8 %conv, i8* %b, align 1
ret void
-; CHECK-LABEL: dpConv2ub
-; CHECK: lfd [[LD:[0-9]+]], 0(3)
-; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stxsibx [[CONV]], 0, 4
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: dpConv2ub
-; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
-; CHECK-PWR8-NEXT: stb [[REG]], 0(4)
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @spConv2udw(float* nocapture readonly %a, i64* nocapture %b) {
+; CHECK-LABEL: spConv2udw:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfs 0, 0(3)
+; CHECK-NEXT: xscvdpuxds 2, 0
+; CHECK-NEXT: stxsd 2, 0(4)
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: spConv2udw:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfsx 0, 0, 3
+; CHECK-PWR8-NEXT: xscvdpuxds 0, 0
+; CHECK-PWR8-NEXT: stxsdx 0, 0, 4
+; CHECK-PWR8-NEXT: blr
entry:
%0 = load float, float* %a, align 4
%conv = fptoui float %0 to i64
store i64 %conv, i64* %b, align 8
ret void
-; CHECK-LABEL: spConv2udw
-; CHECK: lfs [[LD:[0-9]+]], 0(3)
-; CHECK-NEXT: xscvdpuxds [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stxsd [[CONV]], 0(4)
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: spConv2udw
-; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: xscvdpuxds [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: stxsdx [[CONV]], 0, 4
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @spConv2uw(float* nocapture readonly %a, i32* nocapture %b) {
+; CHECK-LABEL: spConv2uw:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfs 0, 0(3)
+; CHECK-NEXT: xscvdpuxws 0, 0
+; CHECK-NEXT: stfiwx 0, 0, 4
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: spConv2uw:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfsx 0, 0, 3
+; CHECK-PWR8-NEXT: xscvdpuxws 0, 0
+; CHECK-PWR8-NEXT: stfiwx 0, 0, 4
+; CHECK-PWR8-NEXT: blr
entry:
%0 = load float, float* %a, align 4
%conv = fptoui float %0 to i32
store i32 %conv, i32* %b, align 4
ret void
-; CHECK-LABEL: spConv2uw
-; CHECK: lfs [[LD:[0-9]+]], 0(3)
-; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stfiwx [[CONV]], 0, 4
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: spConv2uw
-; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: stfiwx [[CONV]], 0, 4
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @spConv2uhw(float* nocapture readonly %a, i16* nocapture %b) {
+; CHECK-LABEL: spConv2uhw:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfs 0, 0(3)
+; CHECK-NEXT: xscvdpuxws 0, 0
+; CHECK-NEXT: stxsihx 0, 0, 4
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: spConv2uhw:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfsx 0, 0, 3
+; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
+; CHECK-PWR8-NEXT: mffprwz 3, 0
+; CHECK-PWR8-NEXT: sth 3, 0(4)
+; CHECK-PWR8-NEXT: blr
entry:
%0 = load float, float* %a, align 4
%conv = fptoui float %0 to i16
store i16 %conv, i16* %b, align 2
ret void
-; CHECK-LABEL: spConv2uhw
-; CHECK: lfs [[LD:[0-9]+]], 0(3)
-; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stxsihx [[CONV]], 0, 4
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: spConv2uhw
-; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
-; CHECK-PWR8-NEXT: sth [[REG]], 0(4)
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @spConv2ub(float* nocapture readonly %a, i8* nocapture %b) {
+; CHECK-LABEL: spConv2ub:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfs 0, 0(3)
+; CHECK-NEXT: xscvdpuxws 0, 0
+; CHECK-NEXT: stxsibx 0, 0, 4
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: spConv2ub:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfsx 0, 0, 3
+; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
+; CHECK-PWR8-NEXT: mffprwz 3, 0
+; CHECK-PWR8-NEXT: stb 3, 0(4)
+; CHECK-PWR8-NEXT: blr
entry:
%0 = load float, float* %a, align 4
%conv = fptoui float %0 to i8
store i8 %conv, i8* %b, align 1
ret void
-; CHECK-LABEL: spConv2ub
-; CHECK: lfs [[LD:[0-9]+]], 0(3)
-; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stxsibx [[CONV]], 0, 4
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: spConv2ub
-; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
-; CHECK-PWR8-NEXT: stb [[REG]], 0(4)
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @dpConv2udw_x(double* nocapture readonly %a, i64* nocapture %b,
+; CHECK-LABEL: dpConv2udw_x:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfd 0, 0(3)
+; CHECK-NEXT: sldi 3, 5, 3
+; CHECK-NEXT: xscvdpuxds 0, 0
+; CHECK-NEXT: stxsdx 0, 4, 3
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: dpConv2udw_x:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfdx 0, 0, 3
+; CHECK-PWR8-NEXT: sldi 3, 5, 3
+; CHECK-PWR8-NEXT: xscvdpuxds 0, 0
+; CHECK-PWR8-NEXT: stxsdx 0, 4, 3
+; CHECK-PWR8-NEXT: blr
i32 zeroext %idx) {
entry:
%0 = load double, double* %a, align 8
@@ -650,23 +822,26 @@ entry:
store i64 %conv, i64* %arrayidx, align 8
ret void
-; CHECK-LABEL: dpConv2udw_x
-; CHECK: lfd [[LD:[0-9]+]], 0(3)
-; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 3
-; CHECK-NEXT: xscvdpuxds [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stxsdx [[CONV]], 4, [[REG]]
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: dpConv2udw_x
-; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8: sldi [[REG:[0-9]+]], 5, 3
-; CHECK-PWR8-NEXT: xscvdpuxds [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: stxsdx [[CONV]], 4, [[REG]]
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @dpConv2uw_x(double* nocapture readonly %a, i32* nocapture %b,
+; CHECK-LABEL: dpConv2uw_x:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfd 0, 0(3)
+; CHECK-NEXT: sldi 3, 5, 2
+; CHECK-NEXT: xscvdpuxws 0, 0
+; CHECK-NEXT: stfiwx 0, 4, 3
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: dpConv2uw_x:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfdx 0, 0, 3
+; CHECK-PWR8-NEXT: sldi 3, 5, 2
+; CHECK-PWR8-NEXT: xscvdpuxws 0, 0
+; CHECK-PWR8-NEXT: stfiwx 0, 4, 3
+; CHECK-PWR8-NEXT: blr
i32 zeroext %idx) {
entry:
%0 = load double, double* %a, align 8
@@ -676,23 +851,27 @@ entry:
store i32 %conv, i32* %arrayidx, align 4
ret void
-; CHECK-LABEL: dpConv2uw_x
-; CHECK: lfd [[LD:[0-9]+]], 0(3)
-; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 2
-; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stfiwx [[CONV]], 4, [[REG]]
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: dpConv2uw_x
-; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 2
-; CHECK-PWR8-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: stfiwx [[CONV]], 4, [[REG]]
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @dpConv2uhw_x(double* nocapture readonly %a, i16* nocapture %b,
+; CHECK-LABEL: dpConv2uhw_x:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfd 0, 0(3)
+; CHECK-NEXT: sldi 3, 5, 1
+; CHECK-NEXT: xscvdpuxws 0, 0
+; CHECK-NEXT: stxsihx 0, 4, 3
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: dpConv2uhw_x:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfdx 0, 0, 3
+; CHECK-PWR8-NEXT: sldi 5, 5, 1
+; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
+; CHECK-PWR8-NEXT: mffprwz 3, 0
+; CHECK-PWR8-NEXT: sthx 3, 4, 5
+; CHECK-PWR8-NEXT: blr
i32 zeroext %idx) {
entry:
%0 = load double, double* %a, align 8
@@ -702,24 +881,25 @@ entry:
store i16 %conv, i16* %arrayidx, align 2
ret void
-; CHECK-LABEL: dpConv2uhw_x
-; CHECK: lfd [[LD:[0-9]+]], 0(3)
-; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 1
-; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stxsihx [[CONV]], 4, [[REG]]
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: dpConv2uhw_x
-; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1
-; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
-; CHECK-PWR8-NEXT: sthx [[REG]], 4, 5
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @dpConv2ub_x(double* nocapture readonly %a, i8* nocapture %b,
+; CHECK-LABEL: dpConv2ub_x:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfd 0, 0(3)
+; CHECK-NEXT: xscvdpuxws 0, 0
+; CHECK-NEXT: stxsibx 0, 4, 5
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: dpConv2ub_x:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfdx 0, 0, 3
+; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
+; CHECK-PWR8-NEXT: mffprwz 3, 0
+; CHECK-PWR8-NEXT: stbx 3, 4, 5
+; CHECK-PWR8-NEXT: blr
i32 zeroext %idx) {
entry:
%0 = load double, double* %a, align 8
@@ -729,22 +909,26 @@ entry:
store i8 %conv, i8* %arrayidx, align 1
ret void
-; CHECK-LABEL: dpConv2ub_x
-; CHECK: lfd [[LD:[0-9]+]], 0(3)
-; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stxsibx [[CONV]], 4, 5
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: dpConv2ub_x
-; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
-; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @spConv2udw_x(float* nocapture readonly %a, i64* nocapture %b,
+; CHECK-LABEL: spConv2udw_x:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfs 0, 0(3)
+; CHECK-NEXT: xscvdpuxds 0, 0
+; CHECK-NEXT: sldi 5, 5, 3
+; CHECK-NEXT: stxsdx 0, 4, 5
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: spConv2udw_x:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfsx 0, 0, 3
+; CHECK-PWR8-NEXT: sldi 3, 5, 3
+; CHECK-PWR8-NEXT: xscvdpuxds 0, 0
+; CHECK-PWR8-NEXT: stxsdx 0, 4, 3
+; CHECK-PWR8-NEXT: blr
i32 zeroext %idx) {
entry:
%0 = load float, float* %a, align 4
@@ -754,23 +938,26 @@ entry:
store i64 %conv, i64* %arrayidx, align 8
ret void
-; CHECK-LABEL: spConv2udw_x
-; CHECK: lfs [[LD:[0-9]+]], 0(3)
-; CHECK-DAG: sldi [[REG:[0-9]+]], 5, 3
-; CHECK-DAG: xscvdpuxds [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stxsdx [[CONV]], 4, [[REG]]
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: spConv2udw_x
-; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 3
-; CHECK-PWR8-NEXT: xscvdpuxds [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: stxsdx [[CONV]], 4, [[REG]]
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @spConv2uw_x(float* nocapture readonly %a, i32* nocapture %b,
+; CHECK-LABEL: spConv2uw_x:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfs 0, 0(3)
+; CHECK-NEXT: xscvdpuxws 0, 0
+; CHECK-NEXT: sldi 5, 5, 2
+; CHECK-NEXT: stfiwx 0, 4, 5
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: spConv2uw_x:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfsx 0, 0, 3
+; CHECK-PWR8-NEXT: sldi 3, 5, 2
+; CHECK-PWR8-NEXT: xscvdpuxws 0, 0
+; CHECK-PWR8-NEXT: stfiwx 0, 4, 3
+; CHECK-PWR8-NEXT: blr
i32 zeroext %idx) {
entry:
%0 = load float, float* %a, align 4
@@ -780,23 +967,27 @@ entry:
store i32 %conv, i32* %arrayidx, align 4
ret void
-; CHECK-LABEL: spConv2uw_x
-; CHECK: lfs [[LD:[0-9]+]], 0(3)
-; CHECK-DAG: sldi [[REG:[0-9]+]], 5, 2
-; CHECK-DAG: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stfiwx [[CONV]], 4, [[REG]]
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: spConv2uw_x
-; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 2
-; CHECK-PWR8-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: stfiwx [[CONV]], 4, [[REG]]
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @spConv2uhw_x(float* nocapture readonly %a, i16* nocapture %b,
+; CHECK-LABEL: spConv2uhw_x:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfs 0, 0(3)
+; CHECK-NEXT: xscvdpuxws 0, 0
+; CHECK-NEXT: sldi 5, 5, 1
+; CHECK-NEXT: stxsihx 0, 4, 5
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: spConv2uhw_x:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfsx 0, 0, 3
+; CHECK-PWR8-NEXT: sldi 5, 5, 1
+; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
+; CHECK-PWR8-NEXT: mffprwz 3, 0
+; CHECK-PWR8-NEXT: sthx 3, 4, 5
+; CHECK-PWR8-NEXT: blr
i32 zeroext %idx) {
entry:
%0 = load float, float* %a, align 4
@@ -806,24 +997,25 @@ entry:
store i16 %conv, i16* %arrayidx, align 2
ret void
-; CHECK-LABEL: spConv2uhw_x
-; CHECK: lfs [[LD:[0-9]+]], 0(3)
-; CHECK-DAG: sldi [[REG:[0-9]+]], 5, 1
-; CHECK-DAG: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stxsihx [[CONV]], 4, [[REG]]
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: spConv2uhw_x
-; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1
-; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mffprwz [[REG2:[0-9]+]], [[CONV]]
-; CHECK-PWR8-NEXT: sthx [[REG2]], 4, [[REG]]
-; CHECK-PWR8-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @spConv2ub_x(float* nocapture readonly %a, i8* nocapture %b,
+; CHECK-LABEL: spConv2ub_x:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lfs 0, 0(3)
+; CHECK-NEXT: xscvdpuxws 0, 0
+; CHECK-NEXT: stxsibx 0, 4, 5
+; CHECK-NEXT: blr
+;
+; CHECK-PWR8-LABEL: spConv2ub_x:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: lfsx 0, 0, 3
+; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
+; CHECK-PWR8-NEXT: mffprwz 3, 0
+; CHECK-PWR8-NEXT: stbx 3, 4, 5
+; CHECK-PWR8-NEXT: blr
i32 zeroext %idx) {
entry:
%0 = load float, float* %a, align 4
@@ -833,16 +1025,5 @@ entry:
store i8 %conv, i8* %arrayidx, align 1
ret void
-; CHECK-LABEL: spConv2ub_x
-; CHECK: lfs [[LD:[0-9]+]], 0(3)
-; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-NEXT: stxsibx [[CONV]], 4, 5
-; CHECK-NEXT: blr
-; CHECK-PWR8-LABEL: spConv2ub_x
-; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
-; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
-; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5
-; CHECK-PWR8-NEXT: blr
}
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