[PATCH] D91977: [RISCV] Remove unused VM register class

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Nov 23 09:50:00 PST 2020

craig.topper created this revision.
craig.topper added reviewers: evandro, HsiangKai, asb, luismarques, frasercrmck, lenary.
Herald added subscribers: NickHung, apazos, sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya.
Herald added a project: LLVM.
craig.topper requested review of this revision.
Herald added a subscriber: MaskRay.

Nothing references this class today so it looks like some leftover.



Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.td
--- llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -331,13 +331,6 @@
 def VMaskVT : RegisterTypes<[nxv1i1, nxv2i1, nxv4i1, nxv8i1, nxv16i1, nxv32i1]>;
-def VM : RegisterClass<"RISCV", VMaskVT.types, 64, (add
-    (sequence "V%u", 25, 31),
-    (sequence "V%u", 8, 24),
-    (sequence "V%u", 0, 7))> {
-  let Size = 64;
 def VMV0 : RegisterClass<"RISCV", VMaskVT.types, 64, (add V0)> {
   let Size = 64;

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