[PATCH] D90844: [TableGen][SchedModels] Fix read/write variant substitution #2

[Eugene Leviant via Phabricator via llvm-commits]

evgeny777 added inline comments.


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Comment at: llvm/utils/TableGen/CodeGenSchedule.cpp:1362
 
+template <> struct llvm::DenseMapInfo<TransVariant> {
+  static inline TransVariant getEmptyKey() { return {nullptr, 0, 0, 0}; }
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dmgreen wrote:
> Does this need to use a densemap? It seems to be being used to check whether the TransVariant have already been handled. Can it use a set or something simpler for that?
Unfortunately it can't, because we not only need to check for same record definition, but also for same processor index (it's a bug in current implementation to ignore this). This is because same variant record may be shared between different processor models (like ReadAdrBase in ThunderX2T99 and ThunderX3T110)


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  https://reviews.llvm.org/D90844/new/

https://reviews.llvm.org/D90844