[PATCH] D91937: [ISel] Port AArch64 SABD and UABD to DAGCombine

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

What other archs have equivalent instructions?



================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:8869
+  EVT VectorT1 = Op0.getOperand(0).getValueType();
+  EVT VectorT2 = Op1.getOperand(0).getValueType();
+  // Check if vectors are of same type and valid size.
----------------
Rename to VT1 /VT2? I don't think there's anything that technically requires them to be vectors?


================
Comment at: llvm/lib/CodeGen/TargetLoweringBase.cpp:776
     setOperationAction(ISD::RHADDU, VT, Expand);
+    // Abd
+    setOperationAction(ISD::ABDS, VT, Expand);
----------------
// Absolute differences


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91937/new/

https://reviews.llvm.org/D91937