[PATCH] D91120: [DAGCombine][PowerPC] Convert negated abs to trivial arithmetic ops

[Kai Luo via Phabricator via llvm-commits]

lkail updated this revision to Diff 306284.
lkail added a comment.
Herald added subscribers: frasercrmck, luismarques, apazos, sameer.abuasal, pzheng, s.egerton, lenary, Jim, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb.

Removed the hook and added test cases for other arch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91120/new/

https://reviews.llvm.org/D91120

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/neg-abs.ll
  llvm/test/CodeGen/PowerPC/neg-abs.ll
  llvm/test/CodeGen/RISCV/neg-abs.ll


Index: llvm/test/CodeGen/RISCV/neg-abs.ll
===================================================================
--- llvm/test/CodeGen/RISCV/neg-abs.ll
+++ llvm/test/CodeGen/RISCV/neg-abs.ll
@@ -8,9 +8,8 @@
 ; CHECK-LABEL: neg_abs:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    srai a1, a0, 63
-; CHECK-NEXT:    add a0, a0, a1
 ; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    sub a0, a1, a0
 ; CHECK-NEXT:    ret
   %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
   %neg = sub nsw i64 0, %abs
Index: llvm/test/CodeGen/PowerPC/neg-abs.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/neg-abs.ll
+++ llvm/test/CodeGen/PowerPC/neg-abs.ll
@@ -9,9 +9,8 @@
 ; CHECK-LE-LABEL: neg_abs:
 ; CHECK-LE:       # %bb.0:
 ; CHECK-LE-NEXT:    sradi r4, r3, 63
-; CHECK-LE-NEXT:    add r3, r3, r4
 ; CHECK-LE-NEXT:    xor r3, r3, r4
-; CHECK-LE-NEXT:    neg r3, r3
+; CHECK-LE-NEXT:    sub r3, r4, r3
 ; CHECK-LE-NEXT:    blr
   %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
   %neg = sub nsw i64 0, %abs
Index: llvm/test/CodeGen/AArch64/neg-abs.ll
===================================================================
--- llvm/test/CodeGen/AArch64/neg-abs.ll
+++ llvm/test/CodeGen/AArch64/neg-abs.ll
@@ -7,9 +7,9 @@
 define i64 at neg_abs(i64 %x) {
 ; CHECK-LABEL: neg_abs:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    cmp x0, #0 // =0
-; CHECK-NEXT:    cneg x8, x0, mi
-; CHECK-NEXT:    neg x0, x8
+; CHECK-NEXT:    asr x8, x0, #63
+; CHECK-NEXT:    eor x9, x0, x8
+; CHECK-NEXT:    sub x0, x8, x9
 ; CHECK-NEXT:    ret
   %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
   %neg = sub nsw i64 0, %abs
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3209,6 +3209,19 @@
       // 0 - X --> X if X is 0 or the minimum signed value.
       return N1;
     }
+
+    // Convert 0 - abs(x) -> Y = sra (X, size(X)-1); sub (Y, xor (X, Y)).
+    if (N1->getOpcode() == ISD::ABS &&
+        !TLI.isOperationLegalOrCustom(ISD::ABS, VT)) {
+      SDValue X = N1->getOperand(0);
+      SDValue Shift =
+          DAG.getNode(ISD::SRA, DL, VT, X,
+                      DAG.getConstant(BitWidth - 1, DL, getShiftAmountTy(VT)));
+      SDValue Xor = DAG.getNode(ISD::XOR, DL, VT, X, Shift);
+      AddToWorklist(Shift.getNode());
+      AddToWorklist(Xor.getNode());
+      return DAG.getNode(ISD::SUB, DL, VT, Shift, Xor);
+    }
   }
 
   // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)


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