[PATCH] D91931: [RISCV][GlobalISel] Select add i32, i32

[luxufan via Phabricator via llvm-commits]

StephenFan created this revision.
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Support the global instruction selection of add i32, i32.
This patch is the minimal support. And this patch referenced the implementation of ARM and AArch64's GlobalISel.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D91931

Files:
  llvm/lib/Target/RISCV/CMakeLists.txt
  llvm/lib/Target/RISCV/RISCVCallLowering.cpp
  llvm/lib/Target/RISCV/RISCVCallingConv.cpp
  llvm/lib/Target/RISCV/RISCVCallingConv.h
  llvm/lib/Target/RISCV/RISCVCallingConv.td
  llvm/lib/Target/RISCV/RISCVInstructionSelector.cpp
  llvm/lib/Target/RISCV/RISCVLegalizerInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterBankInfo.h
  llvm/test/CodeGen/RISCV/GlobalISel/instruction-select.mir
  llvm/test/CodeGen/RISCV/GlobalISel/irtranslator.ll
  llvm/test/CodeGen/RISCV/GlobalISel/isel.ll
  llvm/test/CodeGen/RISCV/GlobalISel/legalizer.mir
  llvm/test/CodeGen/RISCV/GlobalISel/regbankselect.mir

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