[PATCH] D91449: [RISCV] Add RISCVISD::ROLW/RORW use those for custom legalizing i32 rotl/rotr on RV64IZbb.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D91449#2407814 <https://reviews.llvm.org/D91449#2407814>, @frasercrmck wrote:

> LGTM. We can always revisit the `grev`/`ror` question as it applies both before and after this patch. At any rate, matching `rotl`/`rotr` to `roli` is a more logical default.
>
> One thing: I'm surprised by the lack of test changes involving `rol` - are we missing some coverage?

There is no roli instruction only rori. The non-immediate version wasnt broken since we used riscv_sllw/riscv_srlw in type legalization for non-immediate shifts. ORing those gives the right number of sign bits without a sign_extend_inreg.


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