[PATCH] D91603: [PowerPC] Correct the bit-width definition for some imm operand in td.

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf added a comment.

(Not relevant question) Do we have intrinsics, or any exploitation in library for `darn`?



================
Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.td:1900
 
-def DCBF   : DCB_Form_hint<86, (outs), (ins u5imm:$TH, memrr:$dst),
+def DCBF   : DCB_Form_hint<86, (outs), (ins u3imm:$TH, memrr:$dst),
                       "dcbf $dst, $TH", IIC_LdStDCBF, []>,
----------------
`L` is two bits?


================
Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.td:2435
 
-def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
+def SYNC : XForm_24_sync<31, 598, (outs), (ins u3imm:$L),
                         "sync $L", IIC_LdStSync, []>;
----------------
`sync` only uses 2 bits for `L`? (9th-10th bit)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91603/new/

https://reviews.llvm.org/D91603