[PATCH] D72184: [BPF] support atomic instructions

[Yonghong Song via Phabricator via llvm-commits]

yonghong-song added a comment.

Thanks. Somehow my build is successful. I kind of know what is the possible issue but wonder why I did not hit it.

> Can we please keep barriers out of scope? I think there's a lot of design to be done there and I'd rather just get the core atomics working first.

The reason I put it here is to make *cpu=v4* roughly complete. Because if you adds barrier later we may need to add "cpu=v5", and I want to avoid that. But I agree this is a little bit overwhelming on you and let us discuss in bpf office hour how to proceed.

For the time being, alternatively, you can remove the following code
+let hasSideEffects = 1, mayLoad = 1, mayStore = 1 in {
+  def SYNC : TYPE_LD_ST<BPF_ATOMIC.Value, BPF_DW.Value,
+                        (outs), (ins), "sync", []> {
+    let Inst{7-4} = BPF_BARRIER.Value;
+    let BPFClass = BPF_STX;
+  }
+}
+
+def : Pat<(atomic_fence (timm), (timm)), (SYNC)>;
to workaround compilation issue.


Repository:
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  https://reviews.llvm.org/D72184/new/

https://reviews.llvm.org/D72184