[llvm] 5f0ae23 - [X86][AArch64][RISCV] Pre-commit negated abs test case. NFC.

[Kai Luo via llvm-commits]

Author: Kai Luo
Date: 2020-11-19T02:31:45Z
New Revision: 5f0ae23e71df19e0741d049e6077542b32b6b66a

URL: https://github.com/llvm/llvm-project/commit/5f0ae23e71df19e0741d049e6077542b32b6b66a
DIFF: https://github.com/llvm/llvm-project/commit/5f0ae23e71df19e0741d049e6077542b32b6b66a.diff

LOG: [X86][AArch64][RISCV] Pre-commit negated abs test case. NFC.

Added: 
    llvm/test/CodeGen/AArch64/neg-abs.ll
    llvm/test/CodeGen/RISCV/neg-abs.ll
    llvm/test/CodeGen/X86/neg-abs.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AArch64/neg-abs.ll b/llvm/test/CodeGen/AArch64/neg-abs.ll
new file mode 100644
index 000000000000..3dcb04a8e35f
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/neg-abs.ll
@@ -0,0 +1,17 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs \
+; RUN:   -mtriple=aarch64-unknown-unknown < %s | FileCheck %s
+
+declare i64 @llvm.abs.i64(i64, i1 immarg)
+
+define i64 at neg_abs(i64 %x) {
+; CHECK-LABEL: neg_abs:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmp x0, #0 // =0
+; CHECK-NEXT:    cneg x8, x0, mi
+; CHECK-NEXT:    neg x0, x8
+; CHECK-NEXT:    ret
+  %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
+  %neg = sub nsw i64 0, %abs
+  ret i64 %neg
+}

diff  --git a/llvm/test/CodeGen/RISCV/neg-abs.ll b/llvm/test/CodeGen/RISCV/neg-abs.ll
new file mode 100644
index 000000000000..a1bef473c008
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/neg-abs.ll
@@ -0,0 +1,18 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs \
+; RUN:   -mtriple=riscv64-unknown-unknown < %s | FileCheck %s
+
+declare i64 @llvm.abs.i64(i64, i1 immarg)
+
+define i64 at neg_abs(i64 %x) {
+; CHECK-LABEL: neg_abs:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srai a1, a0, 63
+; CHECK-NEXT:    add a0, a0, a1
+; CHECK-NEXT:    xor a0, a0, a1
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
+  %neg = sub nsw i64 0, %abs
+  ret i64 %neg
+}

diff  --git a/llvm/test/CodeGen/X86/neg-abs.ll b/llvm/test/CodeGen/X86/neg-abs.ll
new file mode 100644
index 000000000000..099aa8bdf792
--- /dev/null
+++ b/llvm/test/CodeGen/X86/neg-abs.ll
@@ -0,0 +1,18 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs \
+; RUN:   -mtriple=x86_64-unknown-unknown < %s | FileCheck %s
+
+declare i64 @llvm.abs.i64(i64, i1 immarg)
+
+define i64 at neg_abs(i64 %x) {
+; CHECK-LABEL: neg_abs:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    negq %rax
+; CHECK-NEXT:    cmovlq %rdi, %rax
+; CHECK-NEXT:    negq %rax
+; CHECK-NEXT:    retq
+  %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
+  %neg = sub nsw i64 0, %abs
+  ret i64 %neg
+}