[PATCH] D90978: [WebAssembly] Support fp reg class in r constraint

[Heejin Ahn via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG803af31e5b29: [WebAssembly] Support fp reg class in r constraint (authored by snek, committed by aheejin).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90978/new/

https://reviews.llvm.org/D90978

Files:
  llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
  llvm/test/CodeGen/WebAssembly/inline-asm.ll


Index: llvm/test/CodeGen/WebAssembly/inline-asm.ll
===================================================================
--- llvm/test/CodeGen/WebAssembly/inline-asm.ll
+++ llvm/test/CodeGen/WebAssembly/inline-asm.ll
@@ -46,6 +46,32 @@
   ret i64 %0
 }
 
+; CHECK-LABEL: foo_float:
+; CHECK-NEXT: .functype foo_float (f32) -> (f32){{$}}
+; CHECK-NEXT: #APP{{$}}
+; CHECK-NEXT: # 0 = aaa(0){{$}}
+; CHECK-NEXT: #NO_APP{{$}}
+; CHECK-NEXT: local.get $push0=, 0{{$}}
+; CHECK-NEXT: return $pop0{{$}}
+define float @foo_float(float %r) {
+entry:
+  %0 = tail call float asm sideeffect "# $0 = aaa($1)", "=r,r"(float %r) #0, !srcloc !0
+  ret float %0
+}
+
+; CHECK-LABEL: foo_double:
+; CHECK-NEXT: .functype foo_double (f64) -> (f64){{$}}
+; CHECK-NEXT: #APP{{$}}
+; CHECK-NEXT: # 0 = aaa(0){{$}}
+; CHECK-NEXT: #NO_APP{{$}}
+; CHECK-NEXT: local.get $push0=, 0{{$}}
+; CHECK-NEXT: return $pop0{{$}}
+define double @foo_double(double %r) {
+entry:
+  %0 = tail call double asm sideeffect "# $0 = aaa($1)", "=r,r"(double %r) #0, !srcloc !0
+  ret double %0
+}
+
 ; CHECK-LABEL: X_i16:
 ; CHECK: foo 1{{$}}
 ; CHECK: local.get $push[[S0:[0-9]+]]=, 0{{$}}
Index: llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
===================================================================
--- llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -563,6 +563,16 @@
         if (VT.getSizeInBits() <= 64)
           return std::make_pair(0U, &WebAssembly::I64RegClass);
       }
+      if (VT.isFloatingPoint() && !VT.isVector()) {
+        switch (VT.getSizeInBits()) {
+        case 32:
+          return std::make_pair(0U, &WebAssembly::F32RegClass);
+        case 64:
+          return std::make_pair(0U, &WebAssembly::F64RegClass);
+        default:
+          break;
+        }
+      }
       break;
     default:
       break;


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