[PATCH] D91712: [RISCV] Use register class VR for V instruction operands directly.

[Hsiangkai Wang via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG44cd03ad041e: [RISCV] Use register class VR for V instruction operands directly. (authored by HsiangKai).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91712/new/

https://reviews.llvm.org/D91712

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/test/MC/RISCV/rvv/invalid.s

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