[PATCH] D90853: [RISCV] Add DAG nodes to represent read/write CSR

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

In D90853#2399517 <https://reviews.llvm.org/D90853#2399517>, @sepavloff wrote:

> Even if there were a way to specify particular register in outputs

You mean make RISCV::X0 the first operand? I don’t understand what the problem is.

> , fake writes to X0 would create false output dependencies, which would require specific treatment. Using instructions without output is a natural way to represent such cases.

LLVM knows it’s a constant register. The correct thing to do IMO is fix any places in LLVM that don’t account for constant registers, if there are any, and then have a generic solution, rather than try and work around any deficiencies by adding special cases to backends every single time it comes up.


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