[PATCH] D90853: [RISCV] Add DAG nodes to represent read/write CSR

[Serge Pavlov via Phabricator via llvm-commits]

sepavloff added a comment.

Even if there were a way to specify particular register in outputs, fake writes to X0 would create false output dependencies, which would require specific treatment. Using instructions without output is a natural way to represent such cases.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D90853/new/

https://reviews.llvm.org/D90853