[PATCH] D91541: [VE] Add lvm/svm intrinsic instructions
Kazushi Marukawa via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 16 06:50:39 PST 2020
kaz7 created this revision.
kaz7 added reviewers: simoll, k-ishizaka.
kaz7 added projects: LLVM, VE.
Herald added subscribers: llvm-commits, hiraditya.
kaz7 requested review of this revision.
Add lvm/svm intrinsic instructions and a regression test. Change
RegisterInfo to specify that VM0/VMP0 are constant and reserved
registers. This modifies a vst regression test, so update it.
Also add pseudo instructions for VM512 register classes
and mechanism to expand them after register allocation.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D91541
Files:
llvm/include/llvm/IR/IntrinsicsVEVL.gen.td
llvm/lib/Target/VE/VEInstrInfo.cpp
llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td
llvm/lib/Target/VE/VEInstrVec.td
llvm/lib/Target/VE/VERegisterInfo.cpp
llvm/test/CodeGen/VE/VELIntrinsics/lvm.ll
llvm/test/CodeGen/VE/VELIntrinsics/vst.ll
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