[PATCH] D89239: [RISCV][PrologEpilogInserter] "Float" emergency spill slots to avoid making them immediately unreachable from the stack pointer

[Alexander Richardson via Phabricator via llvm-commits]

arichardson added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir:1
+# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+# REQUIRES: asserts
----------------
rogfer01 wrote:
> arichardson wrote:
> > sdesmalen wrote:
> > > This test seems quite substantial, is there no simpler IR to test this?
> > This test can definitely be reduced a lot more. Also you could run just this pass and make it a MIR test instead.
> The test is already an MIR test. The YAML representation contains a copy of the IR (which it is required to create essential data structures such as `llvm::Function`). I can remove most of it as I understand adds none to little information here.
> 
> I will look into how to reduce the large amount of machine instructions: part of the difficulty is making sure no register is left for the register scavenger when eliminating the frame index of the problematic stack slot (the one that used to be, before this change, too far from the top of the stack).
> 
> I'll look into this again because I think it is possible to do so.
I meant using -run-pass=prologepilog and using update_mir_checks.py to generate the CHECK lines.

I just ran creduce over your test case and it gave me this:

```
# RUN: llc -mtriple riscv64 -start-before=prologepilog -o - -verify-machineinstrs %s
name:            a
stack:
  - { id: 0 , size: 8, alignment: 4096 }
body:             |
  bb.0:
    $= ADD $, $x10
    SD $x12, $, $x13
    $= DIVU $, $x30
    $= DIVU $, $x29
    $= DIV $, $x15
    $= DIV $, $x14
    $= DIV $, $x1
    $= DIV $, $x7
    $= DIV $, $x6
    $= DIV $, $x31
    $= DIV $, $x28
    $= DIV $, $x5
    $= DIV $, $x17
    $= DIV $, $x16
    $= DIV $x11, $
```

Feeding that into `/bin/llc -mtriple riscv64 -start-before=prologepilog -o - -verify-machineinstrs -stop-before=prologepilog`
 yields this:
```
--- |
  ; ModuleID = '/local/scratch/alr48/cheri/build/llvm-project-build/test-reduce.mir'
  source_filename = "/local/scratch/alr48/cheri/build/llvm-project-build/test-reduce.mir"
  target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
  target triple = "riscv64"

  define void @a() {
  entry:
    unreachable
  }

...
---
name:            a
alignment:       1
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: false
hasWinCFI:       false
registers:       []
liveins:         []
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    4096
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 4294967295
  cvBytesOfCalleeSavedRegisters: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:      []
stack:
  - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 4096,
      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites:       []
constants:       []
machineFunctionInfo: {}
body:             |
  bb.0:
    $noreg = ADD $noreg, $x10
    SD $x12, $noreg, $x13
    $noreg = DIVU $noreg, $x30
    $noreg = DIVU $noreg, $x29
    $noreg = DIV $noreg, $x15
    $noreg = DIV $noreg, $x14
    $noreg = DIV $noreg, $x1
    $noreg = DIV $noreg, $x7
    $noreg = DIV $noreg, $x6
    $noreg = DIV $noreg, $x31
    $noreg = DIV $noreg, $x28
    $noreg = DIV $noreg, $x5
    $noreg = DIV $noreg, $x17
    $noreg = DIV $noreg, $x16
    $noreg = DIV $x11, $noreg

...
```


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89239/new/

https://reviews.llvm.org/D89239