[PATCH] D91346: [AArch64] Add FCMLA AArch64ISD node.

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

OK sure. I was expecting some ISel lowering, to be honest. And perhaps for a vplan patch to appear :)

At a concrete level, matching in CodeGenPrep doesn't sound ideal, unless we expect these to spill over multiple basic blocks a lot of the time. At the moment we could get the same effect by matching in ISel, like any other instruction.

If like I suspect (/hope :)) the goal is to pattern match during vectorization and produce something better there - relying on a "complex multply" intrinsic may not be optimal in terms of the patterns you can recognize. The VCMLA and VCMUL/VCADD operations are more general than that and can match other patterns. Things like conjugates and rotates can modify that. I can see how that would be harder to make look target independent though.


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