[PATCH] D91092: [SVE][CodeGen] Lower scalable masked gathers
Kerry McLaughlin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 12 10:20:10 PST 2020
kmclaughlin updated this revision to Diff 304883.
kmclaughlin edited the summary of this revision.
kmclaughlin added a comment.
- Added the getExtendedGatherOpcode() function, which returns a signed gather load opcode (e.g GLD1_MERGE_ZERO -> GLD1S_MERGE_ZERO)
- Get the extension type of the gather load in LowerMGATHER and use the signed gather opcode returned by getExtendedGatherOpcode() if the extension type is EXTLOAD/SEXTLOAD,
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D91092/new/
https://reviews.llvm.org/D91092
Files:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/test/CodeGen/AArch64/sve-masked-gather-32b-signed-scaled.ll
llvm/test/CodeGen/AArch64/sve-masked-gather-32b-signed-unscaled.ll
llvm/test/CodeGen/AArch64/sve-masked-gather-32b-unsigned-scaled.ll
llvm/test/CodeGen/AArch64/sve-masked-gather-32b-unsigned-unscaled.ll
llvm/test/CodeGen/AArch64/sve-masked-gather-64b-scaled.ll
llvm/test/CodeGen/AArch64/sve-masked-gather-64b-unscaled.ll
llvm/test/CodeGen/X86/masked_gather_scatter.ll
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