[PATCH] D90905: [RISCV] Add an ANDI to shift amount of FSL/FSR instructions

[Craig Topper via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG9ca02d6fe166: [RISCV] Add an ANDI to shift amount of FSL/FSR instructions (authored by craig.topper).
Herald added a subscriber: jrtc27.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90905/new/

https://reviews.llvm.org/D90905

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv32Zbt.ll
  llvm/test/CodeGen/RISCV/rv64Zbt.ll

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