[PATCH] D90905: [RISCV] Add an ANDI to shift amount of FSL/FSR instructions
Fraser Cormack via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 12 03:53:12 PST 2020
frasercrmck accepted this revision.
frasercrmck added a comment.
This revision is now accepted and ready to land.
LGTM.
Out of curiosity, can you use anything like `computeKnownBits` in TableGen patterns or would we have to do something in C++?
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D90905/new/
https://reviews.llvm.org/D90905
More information about the llvm-commits
mailing list