[PATCH] D90905: [RISCV] Add an ANDI to shift amount of FSL/FSR instructions

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck accepted this revision.
frasercrmck added a comment.
This revision is now accepted and ready to land.

LGTM.

Out of curiosity, can you use anything like `computeKnownBits` in TableGen patterns or would we have to do something in C++?


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  https://reviews.llvm.org/D90905/new/

https://reviews.llvm.org/D90905