[PATCH] D91125: [AArch64][GlobalISel] Port some AArch64 target specific MUL combines from SDAG.
Amara Emerson via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 10 11:06:04 PST 2020
aemerson added inline comments.
================
Comment at: llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp:110
+ // TODO: check if extended build vector as well.
+ return MRI.getVRegDef(R)->getOpcode() == TargetOpcode::G_SEXT;
+}
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paquette wrote:
> Should this include G_SEXT_INREG and G_SEXTLOAD as well?
Maybe the inreg, but I don't think the extload should be included.
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Comment at: llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp:157
+ MachineInstr &UseMI = *MRI.use_instr_begin(Dst);
+ if (UseMI.getOpcode() == TargetOpcode::G_ADD ||
+ UseMI.getOpcode() == TargetOpcode::G_SUB)
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paquette wrote:
> Should this be conservative around G_ICMP as well? It can be selected using SUBS/ADDS.
Can a G_MUL be folded into an icmp?
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Comment at: llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp:225
+ }
+ // B.buildCopy(DstReg, Res.getReg(0));
+ Res->getOperand(0).setReg(DstReg);
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paquette wrote:
> Remove?
This should probably actually be the copy, since we shouldn't be modifying an instruction without notifying the observer.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D91125/new/
https://reviews.llvm.org/D91125
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