[PATCH] D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1548
+    // With no VL operator in the pseudo, do not modify VL (rd = X0, rs1 = X0).
+    MIB.addReg(RISCV::X0, RegState::Dead)
+       .addReg(RISCV::X0, RegState::Kill);
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I think this does need RegState::Define, but this path isn't exercised in this patch.

I found that AArch64 has a pass (AArch64DeadRegisterDefinitionsPass) that replaces defs of some instructions with WZR(their zero register). So I guess its not unprecedented.


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  https://reviews.llvm.org/D89449/new/

https://reviews.llvm.org/D89449