[llvm] 0ad4d04 - [AMDGPU] Remove an unused return value. NFC.
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 10 01:15:27 PST 2020
Author: Jay Foad
Date: 2020-11-10T09:15:14Z
New Revision: 0ad4d0400260ad7acaa08206181a6db4f3060947
URL: https://github.com/llvm/llvm-project/commit/0ad4d0400260ad7acaa08206181a6db4f3060947
DIFF: https://github.com/llvm/llvm-project/commit/0ad4d0400260ad7acaa08206181a6db4f3060947.diff
LOG: [AMDGPU] Remove an unused return value. NFC.
Differential Revision: https://reviews.llvm.org/D91063
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
index 989937a597fb..b3bafc5b2720 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
@@ -13,11 +13,11 @@
using namespace llvm;
using namespace MIPatternMatch;
-std::tuple<Register, unsigned, MachineInstr *>
+std::pair<Register, unsigned>
AMDGPU::getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg) {
MachineInstr *Def = getDefIgnoringCopies(Reg, MRI);
if (!Def)
- return std::make_tuple(Reg, 0, nullptr);
+ return std::make_pair(Reg, 0);
if (Def->getOpcode() == TargetOpcode::G_CONSTANT) {
unsigned Offset;
@@ -27,21 +27,21 @@ AMDGPU::getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg) {
else
Offset = Op.getCImm()->getZExtValue();
- return std::make_tuple(Register(), Offset, Def);
+ return std::make_pair(Register(), Offset);
}
int64_t Offset;
if (Def->getOpcode() == TargetOpcode::G_ADD) {
// TODO: Handle G_OR used for add case
if (mi_match(Def->getOperand(2).getReg(), MRI, m_ICst(Offset)))
- return std::make_tuple(Def->getOperand(1).getReg(), Offset, Def);
+ return std::make_pair(Def->getOperand(1).getReg(), Offset);
// FIXME: matcher should ignore copies
if (mi_match(Def->getOperand(2).getReg(), MRI, m_Copy(m_ICst(Offset))))
- return std::make_tuple(Def->getOperand(1).getReg(), Offset, Def);
+ return std::make_pair(Def->getOperand(1).getReg(), Offset);
}
- return std::make_tuple(Reg, 0, Def);
+ return std::make_pair(Reg, 0);
}
bool AMDGPU::isLegalVOP3PShuffleMask(ArrayRef<int> Mask) {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h
index 87bb88cec502..12c545561857 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h
@@ -19,8 +19,8 @@ class MachineRegisterInfo;
namespace AMDGPU {
-/// Returns Base register, constant offset, and offset def point.
-std::tuple<Register, unsigned, MachineInstr *>
+/// Returns base register and constant offset.
+std::pair<Register, unsigned>
getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg);
bool isLegalVOP3PShuffleMask(ArrayRef<int> Mask);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 5e34788fefc6..638ec0e7ce06 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -1353,8 +1353,8 @@ bool AMDGPUInstructionSelector::selectDSGWSIntrinsic(MachineInstr &MI,
BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::S_MOV_B32), AMDGPU::M0)
.addImm(0);
} else {
- std::tie(BaseOffset, ImmOffset, OffsetDef)
- = AMDGPU::getBaseWithConstantOffset(*MRI, BaseOffset);
+ std::tie(BaseOffset, ImmOffset) =
+ AMDGPU::getBaseWithConstantOffset(*MRI, BaseOffset);
if (Readfirstlane) {
// We have the constant offset now, so put the readfirstlane back on the
@@ -2573,10 +2573,8 @@ computeIndirectRegIndex(MachineRegisterInfo &MRI,
unsigned EltSize) {
Register IdxBaseReg;
int Offset;
- MachineInstr *Unused;
- std::tie(IdxBaseReg, Offset, Unused)
- = AMDGPU::getBaseWithConstantOffset(MRI, IdxReg);
+ std::tie(IdxBaseReg, Offset) = AMDGPU::getBaseWithConstantOffset(MRI, IdxReg);
if (IdxBaseReg == AMDGPU::NoRegister) {
// This will happen if the index is a known constant. This should ordinarily
// be legalized out, but handle it as a register just in case.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index c405c272ee53..1bdf60960ba3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -3488,11 +3488,10 @@ AMDGPULegalizerInfo::splitBufferOffsets(MachineIRBuilder &B,
const unsigned MaxImm = 4095;
Register BaseReg;
unsigned TotalConstOffset;
- MachineInstr *OffsetDef;
const LLT S32 = LLT::scalar(32);
- std::tie(BaseReg, TotalConstOffset, OffsetDef)
- = AMDGPU::getBaseWithConstantOffset(*B.getMRI(), OrigOffset);
+ std::tie(BaseReg, TotalConstOffset) =
+ AMDGPU::getBaseWithConstantOffset(*B.getMRI(), OrigOffset);
unsigned ImmOffset = TotalConstOffset;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index d79828de1d76..6168b50f9cef 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -1347,10 +1347,9 @@ static unsigned setBufferOffsets(MachineIRBuilder &B,
Register Base;
unsigned Offset;
- MachineInstr *Unused;
- std::tie(Base, Offset, Unused)
- = AMDGPU::getBaseWithConstantOffset(*MRI, CombinedOffset);
+ std::tie(Base, Offset) =
+ AMDGPU::getBaseWithConstantOffset(*MRI, CombinedOffset);
uint32_t SOffset, ImmOffset;
if (Offset > 0 && AMDGPU::splitMUBUFOffset(Offset, SOffset, ImmOffset,
@@ -2708,8 +2707,7 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
Register BaseIdxReg;
unsigned ConstOffset;
- MachineInstr *OffsetDef;
- std::tie(BaseIdxReg, ConstOffset, OffsetDef) =
+ std::tie(BaseIdxReg, ConstOffset) =
AMDGPU::getBaseWithConstantOffset(MRI, MI.getOperand(2).getReg());
// See if the index is an add of a constant which will be foldable by moving
@@ -2840,9 +2838,8 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
Register BaseIdxReg;
unsigned ConstOffset;
- MachineInstr *OffsetDef;
- std::tie(BaseIdxReg, ConstOffset, OffsetDef) =
- AMDGPU::getBaseWithConstantOffset(MRI, MI.getOperand(3).getReg());
+ std::tie(BaseIdxReg, ConstOffset) =
+ AMDGPU::getBaseWithConstantOffset(MRI, MI.getOperand(3).getReg());
// See if the index is an add of a constant which will be foldable by moving
// the base register of the index later if this is going to be executed in a
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