[llvm] d631e52 - [testing] Add exhaustive ULT/UGT vector CTPOP to AArch64 and PPC
David Zarzycki via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 9 07:34:44 PST 2020
Author: David Zarzycki
Date: 2020-11-09T10:34:01-05:00
New Revision: d631e5240c9a8ed6bc62e638b72214d030d564aa
URL: https://github.com/llvm/llvm-project/commit/d631e5240c9a8ed6bc62e638b72214d030d564aa
DIFF: https://github.com/llvm/llvm-project/commit/d631e5240c9a8ed6bc62e638b72214d030d564aa.diff
LOG: [testing] Add exhaustive ULT/UGT vector CTPOP to AArch64 and PPC
This to help review the impact of https://reviews.llvm.org/D89952 which
allows targets to fine tune what SelectionDAG does when vector CTPOP is
not legal.
Added:
llvm/test/CodeGen/AArch64/vector-popcnt-128-ult-ugt.ll
llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/vector-popcnt-128-ult-ugt.ll b/llvm/test/CodeGen/AArch64/vector-popcnt-128-ult-ugt.ll
new file mode 100644
index 000000000000..c95bf9eda1c9
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/vector-popcnt-128-ult-ugt.ll
@@ -0,0 +1,3552 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-unknown- | FileCheck %s
+
+define <16 x i8> @ugt_1_v16i8(<16 x i8> %0) {
+; CHECK-LABEL: ugt_1_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: movi v1.16b, #1
+; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
+ %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
+ %3 = icmp ugt <16 x i8> %2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+ %4 = sext <16 x i1> %3 to <16 x i8>
+ ret <16 x i8> %4
+}
+
+define <16 x i8> @ult_2_v16i8(<16 x i8> %0) {
+; CHECK-LABEL: ult_2_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: movi v1.16b, #2
+; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b
+; CHECK-NEXT: ret
+ %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
+ %3 = icmp ult <16 x i8> %2, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
+ %4 = sext <16 x i1> %3 to <16 x i8>
+ ret <16 x i8> %4
+}
+
+define <16 x i8> @ugt_2_v16i8(<16 x i8> %0) {
+; CHECK-LABEL: ugt_2_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: movi v1.16b, #2
+; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
+ %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
+ %3 = icmp ugt <16 x i8> %2, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
+ %4 = sext <16 x i1> %3 to <16 x i8>
+ ret <16 x i8> %4
+}
+
+define <16 x i8> @ult_3_v16i8(<16 x i8> %0) {
+; CHECK-LABEL: ult_3_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: movi v1.16b, #3
+; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b
+; CHECK-NEXT: ret
+ %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
+ %3 = icmp ult <16 x i8> %2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+ %4 = sext <16 x i1> %3 to <16 x i8>
+ ret <16 x i8> %4
+}
+
+define <16 x i8> @ugt_3_v16i8(<16 x i8> %0) {
+; CHECK-LABEL: ugt_3_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: movi v1.16b, #3
+; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
+ %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
+ %3 = icmp ugt <16 x i8> %2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+ %4 = sext <16 x i1> %3 to <16 x i8>
+ ret <16 x i8> %4
+}
+
+define <16 x i8> @ult_4_v16i8(<16 x i8> %0) {
+; CHECK-LABEL: ult_4_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: movi v1.16b, #4
+; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b
+; CHECK-NEXT: ret
+ %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
+ %3 = icmp ult <16 x i8> %2, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
+ %4 = sext <16 x i1> %3 to <16 x i8>
+ ret <16 x i8> %4
+}
+
+define <16 x i8> @ugt_4_v16i8(<16 x i8> %0) {
+; CHECK-LABEL: ugt_4_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: movi v1.16b, #4
+; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
+ %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
+ %3 = icmp ugt <16 x i8> %2, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
+ %4 = sext <16 x i1> %3 to <16 x i8>
+ ret <16 x i8> %4
+}
+
+define <16 x i8> @ult_5_v16i8(<16 x i8> %0) {
+; CHECK-LABEL: ult_5_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: movi v1.16b, #5
+; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b
+; CHECK-NEXT: ret
+ %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
+ %3 = icmp ult <16 x i8> %2, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
+ %4 = sext <16 x i1> %3 to <16 x i8>
+ ret <16 x i8> %4
+}
+
+define <16 x i8> @ugt_5_v16i8(<16 x i8> %0) {
+; CHECK-LABEL: ugt_5_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: movi v1.16b, #5
+; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
+ %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
+ %3 = icmp ugt <16 x i8> %2, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
+ %4 = sext <16 x i1> %3 to <16 x i8>
+ ret <16 x i8> %4
+}
+
+define <16 x i8> @ult_6_v16i8(<16 x i8> %0) {
+; CHECK-LABEL: ult_6_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: movi v1.16b, #6
+; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b
+; CHECK-NEXT: ret
+ %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
+ %3 = icmp ult <16 x i8> %2, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6>
+ %4 = sext <16 x i1> %3 to <16 x i8>
+ ret <16 x i8> %4
+}
+
+define <16 x i8> @ugt_6_v16i8(<16 x i8> %0) {
+; CHECK-LABEL: ugt_6_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: movi v1.16b, #6
+; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
+ %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
+ %3 = icmp ugt <16 x i8> %2, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6>
+ %4 = sext <16 x i1> %3 to <16 x i8>
+ ret <16 x i8> %4
+}
+
+define <16 x i8> @ult_7_v16i8(<16 x i8> %0) {
+; CHECK-LABEL: ult_7_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: movi v1.16b, #7
+; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b
+; CHECK-NEXT: ret
+ %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
+ %3 = icmp ult <16 x i8> %2, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
+ %4 = sext <16 x i1> %3 to <16 x i8>
+ ret <16 x i8> %4
+}
+
+define <8 x i16> @ugt_1_v8i16(<8 x i16> %0) {
+; CHECK-LABEL: ugt_1_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
+; CHECK-NEXT: add v1.8h, v0.8h, v1.8h
+; CHECK-NEXT: cmtst v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ugt <8 x i16> %2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ult_2_v8i16(<8 x i16> %0) {
+; CHECK-LABEL: ult_2_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
+; CHECK-NEXT: add v1.8h, v0.8h, v1.8h
+; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: cmeq v0.8h, v0.8h, #0
+; CHECK-NEXT: ret
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ult <8 x i16> %2, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ugt_2_v8i16(<8 x i16> %0) {
+; CHECK-LABEL: ugt_2_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: movi v1.8h, #2
+; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ugt <8 x i16> %2, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ult_3_v8i16(<8 x i16> %0) {
+; CHECK-LABEL: ult_3_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: movi v1.8h, #3
+; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h
+; CHECK-NEXT: ret
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ult <8 x i16> %2, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ugt_3_v8i16(<8 x i16> %0) {
+; CHECK-LABEL: ugt_3_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: movi v1.8h, #3
+; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ugt <8 x i16> %2, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ult_4_v8i16(<8 x i16> %0) {
+; CHECK-LABEL: ult_4_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: movi v1.8h, #4
+; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h
+; CHECK-NEXT: ret
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ult <8 x i16> %2, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ugt_4_v8i16(<8 x i16> %0) {
+; CHECK-LABEL: ugt_4_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: movi v1.8h, #4
+; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ugt <8 x i16> %2, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ult_5_v8i16(<8 x i16> %0) {
+; CHECK-LABEL: ult_5_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: movi v1.8h, #5
+; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h
+; CHECK-NEXT: ret
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ult <8 x i16> %2, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ugt_5_v8i16(<8 x i16> %0) {
+; CHECK-LABEL: ugt_5_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: movi v1.8h, #5
+; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ugt <8 x i16> %2, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ult_6_v8i16(<8 x i16> %0) {
+; CHECK-LABEL: ult_6_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: movi v1.8h, #6
+; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h
+; CHECK-NEXT: ret
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ult <8 x i16> %2, <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ugt_6_v8i16(<8 x i16> %0) {
+; CHECK-LABEL: ugt_6_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: movi v1.8h, #6
+; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ugt <8 x i16> %2, <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ult_7_v8i16(<8 x i16> %0) {
+; CHECK-LABEL: ult_7_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: movi v1.8h, #7
+; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h
+; CHECK-NEXT: ret
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ult <8 x i16> %2, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ugt_7_v8i16(<8 x i16> %0) {
+; CHECK-LABEL: ugt_7_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: movi v1.8h, #7
+; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ugt <8 x i16> %2, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ult_8_v8i16(<8 x i16> %0) {
+; CHECK-LABEL: ult_8_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: movi v1.8h, #8
+; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h
+; CHECK-NEXT: ret
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ult <8 x i16> %2, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ugt_8_v8i16(<8 x i16> %0) {
+; CHECK-LABEL: ugt_8_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: movi v1.8h, #8
+; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ugt <8 x i16> %2, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ult_9_v8i16(<8 x i16> %0) {
+; CHECK-LABEL: ult_9_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: movi v1.8h, #9
+; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h
+; CHECK-NEXT: ret
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ult <8 x i16> %2, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ugt_9_v8i16(<8 x i16> %0) {
+; CHECK-LABEL: ugt_9_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: movi v1.8h, #9
+; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ugt <8 x i16> %2, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ult_10_v8i16(<8 x i16> %0) {
+; CHECK-LABEL: ult_10_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: movi v1.8h, #10
+; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h
+; CHECK-NEXT: ret
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ult <8 x i16> %2, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ugt_10_v8i16(<8 x i16> %0) {
+; CHECK-LABEL: ugt_10_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: movi v1.8h, #10
+; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ugt <8 x i16> %2, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ult_11_v8i16(<8 x i16> %0) {
+; CHECK-LABEL: ult_11_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: movi v1.8h, #11
+; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h
+; CHECK-NEXT: ret
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ult <8 x i16> %2, <i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ugt_11_v8i16(<8 x i16> %0) {
+; CHECK-LABEL: ugt_11_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: movi v1.8h, #11
+; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ugt <8 x i16> %2, <i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ult_12_v8i16(<8 x i16> %0) {
+; CHECK-LABEL: ult_12_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: movi v1.8h, #12
+; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h
+; CHECK-NEXT: ret
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ult <8 x i16> %2, <i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ugt_12_v8i16(<8 x i16> %0) {
+; CHECK-LABEL: ugt_12_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: movi v1.8h, #12
+; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ugt <8 x i16> %2, <i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ult_13_v8i16(<8 x i16> %0) {
+; CHECK-LABEL: ult_13_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: movi v1.8h, #13
+; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h
+; CHECK-NEXT: ret
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ult <8 x i16> %2, <i16 13, i16 13, i16 13, i16 13, i16 13, i16 13, i16 13, i16 13>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ugt_13_v8i16(<8 x i16> %0) {
+; CHECK-LABEL: ugt_13_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: movi v1.8h, #13
+; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ugt <8 x i16> %2, <i16 13, i16 13, i16 13, i16 13, i16 13, i16 13, i16 13, i16 13>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ult_14_v8i16(<8 x i16> %0) {
+; CHECK-LABEL: ult_14_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: movi v1.8h, #14
+; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h
+; CHECK-NEXT: ret
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ult <8 x i16> %2, <i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ugt_14_v8i16(<8 x i16> %0) {
+; CHECK-LABEL: ugt_14_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: movi v1.8h, #14
+; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ugt <8 x i16> %2, <i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ult_15_v8i16(<8 x i16> %0) {
+; CHECK-LABEL: ult_15_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: movi v1.8h, #15
+; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h
+; CHECK-NEXT: ret
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ult <8 x i16> %2, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <4 x i32> @ugt_1_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_1_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
+; CHECK-NEXT: add v1.4s, v0.4s, v1.4s
+; CHECK-NEXT: cmtst v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 1, i32 1, i32 1, i32 1>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_2_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_2_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
+; CHECK-NEXT: add v1.4s, v0.4s, v1.4s
+; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 2, i32 2, i32 2, i32 2>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_2_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_2_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #2
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 2, i32 2, i32 2, i32 2>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_3_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_3_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #3
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 3, i32 3, i32 3, i32 3>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_3_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_3_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #3
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 3, i32 3, i32 3, i32 3>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_4_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_4_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #4
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 4, i32 4, i32 4, i32 4>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_4_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_4_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #4
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 4, i32 4, i32 4, i32 4>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_5_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_5_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #5
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 5, i32 5, i32 5, i32 5>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_5_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_5_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #5
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 5, i32 5, i32 5, i32 5>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_6_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_6_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #6
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 6, i32 6, i32 6, i32 6>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_6_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_6_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #6
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 6, i32 6, i32 6, i32 6>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_7_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_7_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #7
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 7, i32 7, i32 7, i32 7>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_7_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_7_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #7
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 7, i32 7, i32 7, i32 7>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_8_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_8_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #8
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 8, i32 8, i32 8, i32 8>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_8_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_8_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #8
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 8, i32 8, i32 8, i32 8>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_9_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_9_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #9
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 9, i32 9, i32 9, i32 9>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_9_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_9_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #9
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 9, i32 9, i32 9, i32 9>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_10_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_10_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #10
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 10, i32 10, i32 10, i32 10>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_10_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_10_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #10
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 10, i32 10, i32 10, i32 10>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_11_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_11_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #11
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 11, i32 11, i32 11, i32 11>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_11_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_11_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #11
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 11, i32 11, i32 11, i32 11>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_12_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_12_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #12
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 12, i32 12, i32 12, i32 12>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_12_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_12_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #12
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 12, i32 12, i32 12, i32 12>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_13_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_13_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #13
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 13, i32 13, i32 13, i32 13>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_13_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_13_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #13
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 13, i32 13, i32 13, i32 13>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_14_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_14_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #14
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 14, i32 14, i32 14, i32 14>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_14_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_14_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #14
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 14, i32 14, i32 14, i32 14>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_15_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_15_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #15
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 15, i32 15, i32 15, i32 15>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_15_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_15_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #15
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 15, i32 15, i32 15, i32 15>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_16_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_16_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #16
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 16, i32 16, i32 16, i32 16>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_16_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_16_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #16
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 16, i32 16, i32 16, i32 16>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_17_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_17_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #17
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 17, i32 17, i32 17, i32 17>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_17_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_17_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #17
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 17, i32 17, i32 17, i32 17>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_18_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_18_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #18
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 18, i32 18, i32 18, i32 18>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_18_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_18_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #18
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 18, i32 18, i32 18, i32 18>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_19_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_19_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #19
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 19, i32 19, i32 19, i32 19>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_19_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_19_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #19
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 19, i32 19, i32 19, i32 19>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_20_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_20_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #20
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 20, i32 20, i32 20, i32 20>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_20_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_20_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #20
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 20, i32 20, i32 20, i32 20>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_21_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_21_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #21
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 21, i32 21, i32 21, i32 21>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_21_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_21_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #21
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 21, i32 21, i32 21, i32 21>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_22_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_22_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #22
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 22, i32 22, i32 22, i32 22>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_22_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_22_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #22
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 22, i32 22, i32 22, i32 22>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_23_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_23_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #23
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 23, i32 23, i32 23, i32 23>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_23_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_23_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #23
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 23, i32 23, i32 23, i32 23>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_24_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_24_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #24
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 24, i32 24, i32 24, i32 24>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_24_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_24_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #24
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 24, i32 24, i32 24, i32 24>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_25_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_25_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #25
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 25, i32 25, i32 25, i32 25>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_25_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_25_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #25
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 25, i32 25, i32 25, i32 25>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_26_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_26_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #26
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 26, i32 26, i32 26, i32 26>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_26_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_26_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #26
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 26, i32 26, i32 26, i32 26>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_27_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_27_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #27
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 27, i32 27, i32 27, i32 27>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_27_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_27_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #27
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 27, i32 27, i32 27, i32 27>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_28_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_28_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #28
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 28, i32 28, i32 28, i32 28>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_28_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_28_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #28
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 28, i32 28, i32 28, i32 28>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_29_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_29_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #29
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 29, i32 29, i32 29, i32 29>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_29_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_29_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #29
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 29, i32 29, i32 29, i32 29>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_30_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_30_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #30
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 30, i32 30, i32 30, i32 30>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_30_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ugt_30_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #30
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 30, i32 30, i32 30, i32 30>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_31_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: ult_31_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: movi v1.4s, #31
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 31, i32 31, i32 31, i32 31>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <2 x i64> @ugt_1_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_1_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
+; CHECK-NEXT: add v1.2d, v0.2d, v1.2d
+; CHECK-NEXT: cmtst v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 1, i64 1>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_2_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_2_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
+; CHECK-NEXT: add v1.2d, v0.2d, v1.2d
+; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: cmeq v0.2d, v0.2d, #0
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 2, i64 2>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_2_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_2_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #2
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 2, i64 2>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_3_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_3_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #3
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 3, i64 3>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_3_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_3_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #3
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 3, i64 3>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_4_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_4_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #4
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 4, i64 4>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_4_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_4_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #4
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 4, i64 4>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_5_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_5_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #5
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 5, i64 5>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_5_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_5_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #5
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 5, i64 5>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_6_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_6_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #6
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 6, i64 6>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_6_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_6_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #6
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 6, i64 6>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_7_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_7_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #7
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 7, i64 7>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_7_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_7_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #7
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 7, i64 7>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_8_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_8_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #8
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 8, i64 8>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_8_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_8_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #8
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 8, i64 8>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_9_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_9_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #9
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 9, i64 9>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_9_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_9_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #9
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 9, i64 9>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_10_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_10_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #10
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 10, i64 10>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_10_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_10_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #10
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 10, i64 10>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_11_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_11_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #11
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 11, i64 11>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_11_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_11_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #11
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 11, i64 11>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_12_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_12_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #12
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 12, i64 12>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_12_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_12_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #12
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 12, i64 12>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_13_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_13_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #13
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 13, i64 13>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_13_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_13_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #13
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 13, i64 13>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_14_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_14_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #14
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 14, i64 14>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_14_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_14_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #14
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 14, i64 14>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_15_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_15_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #15
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 15, i64 15>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_15_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_15_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #15
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 15, i64 15>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_16_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_16_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #16
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 16, i64 16>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_16_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_16_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #16
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 16, i64 16>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_17_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_17_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #17
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 17, i64 17>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_17_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_17_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #17
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 17, i64 17>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_18_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_18_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #18
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 18, i64 18>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_18_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_18_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #18
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 18, i64 18>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_19_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_19_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #19
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 19, i64 19>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_19_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_19_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #19
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 19, i64 19>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_20_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_20_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #20
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 20, i64 20>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_20_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_20_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #20
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 20, i64 20>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_21_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_21_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #21
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 21, i64 21>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_21_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_21_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #21
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 21, i64 21>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_22_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_22_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #22
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 22, i64 22>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_22_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_22_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #22
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 22, i64 22>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_23_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_23_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #23
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 23, i64 23>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_23_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_23_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #23
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 23, i64 23>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_24_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_24_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #24
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 24, i64 24>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_24_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_24_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #24
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 24, i64 24>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_25_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_25_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #25
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 25, i64 25>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_25_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_25_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #25
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 25, i64 25>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_26_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_26_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #26
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 26, i64 26>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_26_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_26_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #26
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 26, i64 26>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_27_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_27_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #27
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 27, i64 27>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_27_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_27_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #27
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 27, i64 27>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_28_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_28_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #28
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 28, i64 28>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_28_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_28_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #28
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 28, i64 28>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_29_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_29_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #29
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 29, i64 29>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_29_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_29_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #29
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 29, i64 29>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_30_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_30_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #30
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 30, i64 30>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_30_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_30_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #30
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 30, i64 30>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_31_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_31_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #31
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 31, i64 31>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_31_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_31_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #31
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 31, i64 31>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_32_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_32_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #32
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 32, i64 32>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_32_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_32_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #32
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 32, i64 32>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_33_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_33_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #33
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 33, i64 33>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_33_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_33_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #33
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 33, i64 33>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_34_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_34_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #34
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 34, i64 34>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_34_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_34_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #34
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 34, i64 34>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_35_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_35_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #35
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 35, i64 35>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_35_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_35_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #35
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 35, i64 35>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_36_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_36_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #36
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 36, i64 36>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_36_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_36_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #36
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 36, i64 36>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_37_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_37_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #37
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 37, i64 37>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_37_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_37_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #37
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 37, i64 37>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_38_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_38_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #38
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 38, i64 38>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_38_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_38_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #38
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 38, i64 38>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_39_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_39_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #39
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 39, i64 39>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_39_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_39_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #39
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 39, i64 39>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_40_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_40_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #40
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 40, i64 40>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_40_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_40_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #40
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 40, i64 40>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_41_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_41_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #41
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 41, i64 41>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_41_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_41_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #41
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 41, i64 41>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_42_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_42_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #42
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 42, i64 42>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_42_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_42_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #42
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 42, i64 42>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_43_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_43_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #43
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 43, i64 43>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_43_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_43_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #43
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 43, i64 43>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_44_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_44_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #44
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 44, i64 44>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_44_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_44_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #44
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 44, i64 44>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_45_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_45_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #45
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 45, i64 45>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_45_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_45_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #45
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 45, i64 45>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_46_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_46_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #46
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 46, i64 46>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_46_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_46_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #46
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 46, i64 46>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_47_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_47_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #47
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 47, i64 47>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_47_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_47_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #47
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 47, i64 47>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_48_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_48_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #48
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 48, i64 48>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_48_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_48_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #48
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 48, i64 48>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_49_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_49_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #49
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 49, i64 49>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_49_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_49_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #49
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 49, i64 49>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_50_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_50_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #50
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 50, i64 50>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_50_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_50_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #50
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 50, i64 50>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_51_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_51_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #51
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 51, i64 51>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_51_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_51_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #51
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 51, i64 51>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_52_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_52_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #52
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 52, i64 52>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_52_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_52_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #52
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 52, i64 52>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_53_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_53_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #53
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 53, i64 53>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_53_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_53_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #53
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 53, i64 53>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_54_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_54_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #54
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 54, i64 54>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_54_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_54_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #54
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 54, i64 54>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_55_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_55_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #55
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 55, i64 55>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_55_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_55_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #55
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 55, i64 55>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_56_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_56_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #56
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 56, i64 56>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_56_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_56_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #56
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 56, i64 56>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_57_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_57_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #57
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 57, i64 57>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_57_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_57_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #57
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 57, i64 57>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_58_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_58_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #58
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 58, i64 58>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_58_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_58_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #58
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 58, i64 58>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_59_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_59_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #59
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 59, i64 59>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_59_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_59_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #59
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 59, i64 59>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_60_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_60_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #60
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 60, i64 60>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_60_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_60_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #60
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 60, i64 60>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_61_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_61_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #61
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 61, i64 61>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_61_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_61_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #61
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 61, i64 61>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_62_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_62_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #62
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 62, i64 62>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_62_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ugt_62_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #62
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 62, i64 62>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_63_v2i64(<2 x i64> %0) {
+; CHECK-LABEL: ult_63_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: uaddlp v0.8h, v0.16b
+; CHECK-NEXT: mov w8, #63
+; CHECK-NEXT: uaddlp v0.4s, v0.8h
+; CHECK-NEXT: uaddlp v0.2d, v0.4s
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 63, i64 63>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>)
+declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>)
+declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>)
+declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>)
diff --git a/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll b/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
new file mode 100644
index 000000000000..7acb89df6c87
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
@@ -0,0 +1,28430 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr5 < %s | FileCheck %s --check-prefixes=ANYPWR,PWR5
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr6 < %s | FileCheck %s --check-prefixes=ANYPWR,PWR6
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s --check-prefixes=ANYPWR,PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s --check-prefixes=ANYPWR,PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s --check-prefixes=ANYPWR,PWR9
+
+
+define <16 x i8> @ugt_1_v16i8(<16 x i8> %0) {
+; PWR5-LABEL: ugt_1_v16i8:
+; PWR5: # %bb.0:
+; PWR5-NEXT: vspltisb 3, -1
+; PWR5-NEXT: vaddubm 3, 2, 3
+; PWR5-NEXT: vand 2, 2, 3
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: vcmpequb 2, 2, 3
+; PWR5-NEXT: vnot 2, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_1_v16i8:
+; PWR6: # %bb.0:
+; PWR6-NEXT: vspltisb 3, -1
+; PWR6-NEXT: vaddubm 3, 2, 3
+; PWR6-NEXT: vand 2, 2, 3
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: vcmpequb 2, 2, 3
+; PWR6-NEXT: vnot 2, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_1_v16i8:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisb 3, -1
+; PWR7-NEXT: vaddubm 3, 2, 3
+; PWR7-NEXT: xxland 34, 34, 35
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: vcmpequb 2, 2, 3
+; PWR7-NEXT: xxlnor 34, 34, 34
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_1_v16i8:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisb 3, 1
+; PWR8-NEXT: vpopcntb 2, 2
+; PWR8-NEXT: vcmpgtub 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_1_v16i8:
+; PWR9: # %bb.0:
+; PWR9-NEXT: xxspltib 35, 1
+; PWR9-NEXT: vpopcntb 2, 2
+; PWR9-NEXT: vcmpgtub 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
+ %3 = icmp ugt <16 x i8> %2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+ %4 = sext <16 x i1> %3 to <16 x i8>
+ ret <16 x i8> %4
+}
+
+define <16 x i8> @ult_2_v16i8(<16 x i8> %0) {
+; PWR5-LABEL: ult_2_v16i8:
+; PWR5: # %bb.0:
+; PWR5-NEXT: vspltisb 3, -1
+; PWR5-NEXT: vaddubm 3, 2, 3
+; PWR5-NEXT: vand 2, 2, 3
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: vcmpequb 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_2_v16i8:
+; PWR6: # %bb.0:
+; PWR6-NEXT: vspltisb 3, -1
+; PWR6-NEXT: vaddubm 3, 2, 3
+; PWR6-NEXT: vand 2, 2, 3
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: vcmpequb 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_2_v16i8:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisb 3, -1
+; PWR7-NEXT: vaddubm 3, 2, 3
+; PWR7-NEXT: xxland 34, 34, 35
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: vcmpequb 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_2_v16i8:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisb 3, 2
+; PWR8-NEXT: vpopcntb 2, 2
+; PWR8-NEXT: vcmpgtub 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_2_v16i8:
+; PWR9: # %bb.0:
+; PWR9-NEXT: xxspltib 35, 2
+; PWR9-NEXT: vpopcntb 2, 2
+; PWR9-NEXT: vcmpgtub 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
+ %3 = icmp ult <16 x i8> %2, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
+ %4 = sext <16 x i1> %3 to <16 x i8>
+ ret <16 x i8> %4
+}
+
+define <16 x i8> @ugt_2_v16i8(<16 x i8> %0) {
+; PWR5-LABEL: ugt_2_v16i8:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI2_0 at toc@ha
+; PWR5-NEXT: vspltisb 3, 1
+; PWR5-NEXT: addi 3, 3, .LCPI2_0 at toc@l
+; PWR5-NEXT: vsrb 3, 2, 3
+; PWR5-NEXT: lvx 4, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI2_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI2_1 at toc@l
+; PWR5-NEXT: vspltisb 5, 2
+; PWR5-NEXT: vand 3, 3, 4
+; PWR5-NEXT: lvx 4, 0, 3
+; PWR5-NEXT: vsububm 2, 2, 3
+; PWR5-NEXT: vand 3, 2, 4
+; PWR5-NEXT: vsrb 2, 2, 5
+; PWR5-NEXT: vand 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 4
+; PWR5-NEXT: vaddubm 2, 3, 2
+; PWR5-NEXT: vsrb 3, 2, 4
+; PWR5-NEXT: vspltisb 4, 15
+; PWR5-NEXT: vaddubm 2, 2, 3
+; PWR5-NEXT: vand 2, 2, 4
+; PWR5-NEXT: vcmpgtub 2, 2, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_2_v16i8:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI2_0 at toc@ha
+; PWR6-NEXT: vspltisb 3, 1
+; PWR6-NEXT: addi 3, 3, .LCPI2_0 at toc@l
+; PWR6-NEXT: vsrb 3, 2, 3
+; PWR6-NEXT: lvx 4, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI2_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI2_1 at toc@l
+; PWR6-NEXT: vspltisb 5, 2
+; PWR6-NEXT: vand 3, 3, 4
+; PWR6-NEXT: lvx 4, 0, 3
+; PWR6-NEXT: vsububm 2, 2, 3
+; PWR6-NEXT: vand 3, 2, 4
+; PWR6-NEXT: vsrb 2, 2, 5
+; PWR6-NEXT: vand 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 4
+; PWR6-NEXT: vaddubm 2, 3, 2
+; PWR6-NEXT: vsrb 3, 2, 4
+; PWR6-NEXT: vspltisb 4, 15
+; PWR6-NEXT: vaddubm 2, 2, 3
+; PWR6-NEXT: vand 2, 2, 4
+; PWR6-NEXT: vcmpgtub 2, 2, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_2_v16i8:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI2_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI2_0 at toc@l
+; PWR7-NEXT: vspltisb 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI2_1 at toc@ha
+; PWR7-NEXT: vspltisb 5, 4
+; PWR7-NEXT: vsrb 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI2_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsububm 2, 2, 3
+; PWR7-NEXT: vsrb 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vaddubm 2, 2, 3
+; PWR7-NEXT: vsrb 3, 2, 5
+; PWR7-NEXT: vspltisb 5, 15
+; PWR7-NEXT: vaddubm 2, 2, 3
+; PWR7-NEXT: xxland 34, 34, 37
+; PWR7-NEXT: vcmpgtub 2, 2, 4
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_2_v16i8:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisb 3, 2
+; PWR8-NEXT: vpopcntb 2, 2
+; PWR8-NEXT: vcmpgtub 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_2_v16i8:
+; PWR9: # %bb.0:
+; PWR9-NEXT: xxspltib 35, 2
+; PWR9-NEXT: vpopcntb 2, 2
+; PWR9-NEXT: vcmpgtub 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
+ %3 = icmp ugt <16 x i8> %2, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
+ %4 = sext <16 x i1> %3 to <16 x i8>
+ ret <16 x i8> %4
+}
+
+define <16 x i8> @ult_3_v16i8(<16 x i8> %0) {
+; PWR5-LABEL: ult_3_v16i8:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI3_0 at toc@ha
+; PWR5-NEXT: vspltisb 3, 1
+; PWR5-NEXT: addi 3, 3, .LCPI3_0 at toc@l
+; PWR5-NEXT: vsrb 3, 2, 3
+; PWR5-NEXT: lvx 4, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI3_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI3_1 at toc@l
+; PWR5-NEXT: vspltisb 5, 2
+; PWR5-NEXT: vand 3, 3, 4
+; PWR5-NEXT: lvx 4, 0, 3
+; PWR5-NEXT: vsububm 2, 2, 3
+; PWR5-NEXT: vand 3, 2, 4
+; PWR5-NEXT: vsrb 2, 2, 5
+; PWR5-NEXT: vand 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 4
+; PWR5-NEXT: vaddubm 2, 3, 2
+; PWR5-NEXT: vsrb 3, 2, 4
+; PWR5-NEXT: vspltisb 4, 15
+; PWR5-NEXT: vaddubm 2, 2, 3
+; PWR5-NEXT: vspltisb 3, 3
+; PWR5-NEXT: vand 2, 2, 4
+; PWR5-NEXT: vcmpgtub 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_3_v16i8:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI3_0 at toc@ha
+; PWR6-NEXT: vspltisb 3, 1
+; PWR6-NEXT: addi 3, 3, .LCPI3_0 at toc@l
+; PWR6-NEXT: vsrb 3, 2, 3
+; PWR6-NEXT: lvx 4, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI3_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI3_1 at toc@l
+; PWR6-NEXT: vspltisb 5, 2
+; PWR6-NEXT: vand 3, 3, 4
+; PWR6-NEXT: lvx 4, 0, 3
+; PWR6-NEXT: vsububm 2, 2, 3
+; PWR6-NEXT: vand 3, 2, 4
+; PWR6-NEXT: vsrb 2, 2, 5
+; PWR6-NEXT: vand 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 4
+; PWR6-NEXT: vaddubm 2, 3, 2
+; PWR6-NEXT: vsrb 3, 2, 4
+; PWR6-NEXT: vspltisb 4, 15
+; PWR6-NEXT: vaddubm 2, 2, 3
+; PWR6-NEXT: vspltisb 3, 3
+; PWR6-NEXT: vand 2, 2, 4
+; PWR6-NEXT: vcmpgtub 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_3_v16i8:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI3_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI3_0 at toc@l
+; PWR7-NEXT: vspltisb 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI3_1 at toc@ha
+; PWR7-NEXT: vsrb 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI3_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsububm 2, 2, 3
+; PWR7-NEXT: vsrb 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisb 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vaddubm 2, 2, 3
+; PWR7-NEXT: vsrb 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 15
+; PWR7-NEXT: vaddubm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 3
+; PWR7-NEXT: xxland 34, 34, 36
+; PWR7-NEXT: vcmpgtub 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_3_v16i8:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisb 3, 3
+; PWR8-NEXT: vpopcntb 2, 2
+; PWR8-NEXT: vcmpgtub 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_3_v16i8:
+; PWR9: # %bb.0:
+; PWR9-NEXT: xxspltib 35, 3
+; PWR9-NEXT: vpopcntb 2, 2
+; PWR9-NEXT: vcmpgtub 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
+ %3 = icmp ult <16 x i8> %2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+ %4 = sext <16 x i1> %3 to <16 x i8>
+ ret <16 x i8> %4
+}
+
+define <16 x i8> @ugt_3_v16i8(<16 x i8> %0) {
+; PWR5-LABEL: ugt_3_v16i8:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI4_0 at toc@ha
+; PWR5-NEXT: vspltisb 3, 1
+; PWR5-NEXT: addi 3, 3, .LCPI4_0 at toc@l
+; PWR5-NEXT: vsrb 3, 2, 3
+; PWR5-NEXT: lvx 4, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI4_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI4_1 at toc@l
+; PWR5-NEXT: vspltisb 5, 2
+; PWR5-NEXT: vand 3, 3, 4
+; PWR5-NEXT: lvx 4, 0, 3
+; PWR5-NEXT: vsububm 2, 2, 3
+; PWR5-NEXT: vand 3, 2, 4
+; PWR5-NEXT: vsrb 2, 2, 5
+; PWR5-NEXT: vand 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 4
+; PWR5-NEXT: vaddubm 2, 3, 2
+; PWR5-NEXT: vsrb 3, 2, 4
+; PWR5-NEXT: vspltisb 4, 15
+; PWR5-NEXT: vaddubm 2, 2, 3
+; PWR5-NEXT: vspltisb 3, 3
+; PWR5-NEXT: vand 2, 2, 4
+; PWR5-NEXT: vcmpgtub 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_3_v16i8:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI4_0 at toc@ha
+; PWR6-NEXT: vspltisb 3, 1
+; PWR6-NEXT: addi 3, 3, .LCPI4_0 at toc@l
+; PWR6-NEXT: vsrb 3, 2, 3
+; PWR6-NEXT: lvx 4, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI4_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI4_1 at toc@l
+; PWR6-NEXT: vspltisb 5, 2
+; PWR6-NEXT: vand 3, 3, 4
+; PWR6-NEXT: lvx 4, 0, 3
+; PWR6-NEXT: vsububm 2, 2, 3
+; PWR6-NEXT: vand 3, 2, 4
+; PWR6-NEXT: vsrb 2, 2, 5
+; PWR6-NEXT: vand 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 4
+; PWR6-NEXT: vaddubm 2, 3, 2
+; PWR6-NEXT: vsrb 3, 2, 4
+; PWR6-NEXT: vspltisb 4, 15
+; PWR6-NEXT: vaddubm 2, 2, 3
+; PWR6-NEXT: vspltisb 3, 3
+; PWR6-NEXT: vand 2, 2, 4
+; PWR6-NEXT: vcmpgtub 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_3_v16i8:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI4_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI4_0 at toc@l
+; PWR7-NEXT: vspltisb 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI4_1 at toc@ha
+; PWR7-NEXT: vsrb 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI4_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsububm 2, 2, 3
+; PWR7-NEXT: vsrb 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisb 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vaddubm 2, 2, 3
+; PWR7-NEXT: vsrb 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 15
+; PWR7-NEXT: vaddubm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 3
+; PWR7-NEXT: xxland 34, 34, 36
+; PWR7-NEXT: vcmpgtub 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_3_v16i8:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisb 3, 3
+; PWR8-NEXT: vpopcntb 2, 2
+; PWR8-NEXT: vcmpgtub 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_3_v16i8:
+; PWR9: # %bb.0:
+; PWR9-NEXT: xxspltib 35, 3
+; PWR9-NEXT: vpopcntb 2, 2
+; PWR9-NEXT: vcmpgtub 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
+ %3 = icmp ugt <16 x i8> %2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+ %4 = sext <16 x i1> %3 to <16 x i8>
+ ret <16 x i8> %4
+}
+
+define <16 x i8> @ult_4_v16i8(<16 x i8> %0) {
+; PWR5-LABEL: ult_4_v16i8:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI5_0 at toc@ha
+; PWR5-NEXT: vspltisb 3, 1
+; PWR5-NEXT: addi 3, 3, .LCPI5_0 at toc@l
+; PWR5-NEXT: vsrb 3, 2, 3
+; PWR5-NEXT: lvx 4, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI5_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI5_1 at toc@l
+; PWR5-NEXT: vspltisb 5, 2
+; PWR5-NEXT: vand 3, 3, 4
+; PWR5-NEXT: lvx 4, 0, 3
+; PWR5-NEXT: vsububm 2, 2, 3
+; PWR5-NEXT: vand 3, 2, 4
+; PWR5-NEXT: vsrb 2, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vand 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 4
+; PWR5-NEXT: vaddubm 2, 3, 2
+; PWR5-NEXT: vsrb 3, 2, 4
+; PWR5-NEXT: vaddubm 2, 2, 3
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vcmpgtub 2, 4, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_4_v16i8:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI5_0 at toc@ha
+; PWR6-NEXT: vspltisb 3, 1
+; PWR6-NEXT: addi 3, 3, .LCPI5_0 at toc@l
+; PWR6-NEXT: vsrb 3, 2, 3
+; PWR6-NEXT: lvx 4, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI5_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI5_1 at toc@l
+; PWR6-NEXT: vspltisb 5, 2
+; PWR6-NEXT: vand 3, 3, 4
+; PWR6-NEXT: lvx 4, 0, 3
+; PWR6-NEXT: vsububm 2, 2, 3
+; PWR6-NEXT: vand 3, 2, 4
+; PWR6-NEXT: vsrb 2, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vand 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 4
+; PWR6-NEXT: vaddubm 2, 3, 2
+; PWR6-NEXT: vsrb 3, 2, 4
+; PWR6-NEXT: vaddubm 2, 2, 3
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vcmpgtub 2, 4, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_4_v16i8:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI5_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI5_0 at toc@l
+; PWR7-NEXT: vspltisb 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI5_1 at toc@ha
+; PWR7-NEXT: vspltisb 5, 15
+; PWR7-NEXT: vsrb 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI5_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsububm 2, 2, 3
+; PWR7-NEXT: vsrb 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisb 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vaddubm 2, 2, 3
+; PWR7-NEXT: vsrb 3, 2, 4
+; PWR7-NEXT: vaddubm 2, 2, 3
+; PWR7-NEXT: xxland 34, 34, 37
+; PWR7-NEXT: vcmpgtub 2, 4, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_4_v16i8:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisb 3, 4
+; PWR8-NEXT: vpopcntb 2, 2
+; PWR8-NEXT: vcmpgtub 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_4_v16i8:
+; PWR9: # %bb.0:
+; PWR9-NEXT: xxspltib 35, 4
+; PWR9-NEXT: vpopcntb 2, 2
+; PWR9-NEXT: vcmpgtub 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
+ %3 = icmp ult <16 x i8> %2, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
+ %4 = sext <16 x i1> %3 to <16 x i8>
+ ret <16 x i8> %4
+}
+
+define <16 x i8> @ugt_4_v16i8(<16 x i8> %0) {
+; PWR5-LABEL: ugt_4_v16i8:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI6_0 at toc@ha
+; PWR5-NEXT: vspltisb 3, 1
+; PWR5-NEXT: addi 3, 3, .LCPI6_0 at toc@l
+; PWR5-NEXT: vsrb 3, 2, 3
+; PWR5-NEXT: lvx 4, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI6_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI6_1 at toc@l
+; PWR5-NEXT: vspltisb 5, 2
+; PWR5-NEXT: vand 3, 3, 4
+; PWR5-NEXT: lvx 4, 0, 3
+; PWR5-NEXT: vsububm 2, 2, 3
+; PWR5-NEXT: vand 3, 2, 4
+; PWR5-NEXT: vsrb 2, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vand 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 4
+; PWR5-NEXT: vaddubm 2, 3, 2
+; PWR5-NEXT: vsrb 3, 2, 4
+; PWR5-NEXT: vaddubm 2, 2, 3
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vcmpgtub 2, 2, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_4_v16i8:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI6_0 at toc@ha
+; PWR6-NEXT: vspltisb 3, 1
+; PWR6-NEXT: addi 3, 3, .LCPI6_0 at toc@l
+; PWR6-NEXT: vsrb 3, 2, 3
+; PWR6-NEXT: lvx 4, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI6_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI6_1 at toc@l
+; PWR6-NEXT: vspltisb 5, 2
+; PWR6-NEXT: vand 3, 3, 4
+; PWR6-NEXT: lvx 4, 0, 3
+; PWR6-NEXT: vsububm 2, 2, 3
+; PWR6-NEXT: vand 3, 2, 4
+; PWR6-NEXT: vsrb 2, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vand 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 4
+; PWR6-NEXT: vaddubm 2, 3, 2
+; PWR6-NEXT: vsrb 3, 2, 4
+; PWR6-NEXT: vaddubm 2, 2, 3
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vcmpgtub 2, 2, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_4_v16i8:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI6_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI6_0 at toc@l
+; PWR7-NEXT: vspltisb 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI6_1 at toc@ha
+; PWR7-NEXT: vspltisb 5, 15
+; PWR7-NEXT: vsrb 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI6_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsububm 2, 2, 3
+; PWR7-NEXT: vsrb 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisb 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vaddubm 2, 2, 3
+; PWR7-NEXT: vsrb 3, 2, 4
+; PWR7-NEXT: vaddubm 2, 2, 3
+; PWR7-NEXT: xxland 34, 34, 37
+; PWR7-NEXT: vcmpgtub 2, 2, 4
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_4_v16i8:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisb 3, 4
+; PWR8-NEXT: vpopcntb 2, 2
+; PWR8-NEXT: vcmpgtub 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_4_v16i8:
+; PWR9: # %bb.0:
+; PWR9-NEXT: xxspltib 35, 4
+; PWR9-NEXT: vpopcntb 2, 2
+; PWR9-NEXT: vcmpgtub 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
+ %3 = icmp ugt <16 x i8> %2, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
+ %4 = sext <16 x i1> %3 to <16 x i8>
+ ret <16 x i8> %4
+}
+
+define <16 x i8> @ult_5_v16i8(<16 x i8> %0) {
+; PWR5-LABEL: ult_5_v16i8:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI7_0 at toc@ha
+; PWR5-NEXT: vspltisb 3, 1
+; PWR5-NEXT: addi 3, 3, .LCPI7_0 at toc@l
+; PWR5-NEXT: vsrb 3, 2, 3
+; PWR5-NEXT: lvx 4, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI7_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI7_1 at toc@l
+; PWR5-NEXT: vspltisb 5, 2
+; PWR5-NEXT: vand 3, 3, 4
+; PWR5-NEXT: lvx 4, 0, 3
+; PWR5-NEXT: vsububm 2, 2, 3
+; PWR5-NEXT: vand 3, 2, 4
+; PWR5-NEXT: vsrb 2, 2, 5
+; PWR5-NEXT: vand 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 4
+; PWR5-NEXT: vaddubm 2, 3, 2
+; PWR5-NEXT: vsrb 3, 2, 4
+; PWR5-NEXT: vspltisb 4, 15
+; PWR5-NEXT: vaddubm 2, 2, 3
+; PWR5-NEXT: vspltisb 3, 5
+; PWR5-NEXT: vand 2, 2, 4
+; PWR5-NEXT: vcmpgtub 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_5_v16i8:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI7_0 at toc@ha
+; PWR6-NEXT: vspltisb 3, 1
+; PWR6-NEXT: addi 3, 3, .LCPI7_0 at toc@l
+; PWR6-NEXT: vsrb 3, 2, 3
+; PWR6-NEXT: lvx 4, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI7_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI7_1 at toc@l
+; PWR6-NEXT: vspltisb 5, 2
+; PWR6-NEXT: vand 3, 3, 4
+; PWR6-NEXT: lvx 4, 0, 3
+; PWR6-NEXT: vsububm 2, 2, 3
+; PWR6-NEXT: vand 3, 2, 4
+; PWR6-NEXT: vsrb 2, 2, 5
+; PWR6-NEXT: vand 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 4
+; PWR6-NEXT: vaddubm 2, 3, 2
+; PWR6-NEXT: vsrb 3, 2, 4
+; PWR6-NEXT: vspltisb 4, 15
+; PWR6-NEXT: vaddubm 2, 2, 3
+; PWR6-NEXT: vspltisb 3, 5
+; PWR6-NEXT: vand 2, 2, 4
+; PWR6-NEXT: vcmpgtub 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_5_v16i8:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI7_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI7_0 at toc@l
+; PWR7-NEXT: vspltisb 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI7_1 at toc@ha
+; PWR7-NEXT: vsrb 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI7_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsububm 2, 2, 3
+; PWR7-NEXT: vsrb 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisb 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vaddubm 2, 2, 3
+; PWR7-NEXT: vsrb 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 15
+; PWR7-NEXT: vaddubm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 5
+; PWR7-NEXT: xxland 34, 34, 36
+; PWR7-NEXT: vcmpgtub 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_5_v16i8:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisb 3, 5
+; PWR8-NEXT: vpopcntb 2, 2
+; PWR8-NEXT: vcmpgtub 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_5_v16i8:
+; PWR9: # %bb.0:
+; PWR9-NEXT: xxspltib 35, 5
+; PWR9-NEXT: vpopcntb 2, 2
+; PWR9-NEXT: vcmpgtub 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
+ %3 = icmp ult <16 x i8> %2, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
+ %4 = sext <16 x i1> %3 to <16 x i8>
+ ret <16 x i8> %4
+}
+
+define <16 x i8> @ugt_5_v16i8(<16 x i8> %0) {
+; PWR5-LABEL: ugt_5_v16i8:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI8_0 at toc@ha
+; PWR5-NEXT: vspltisb 3, 1
+; PWR5-NEXT: addi 3, 3, .LCPI8_0 at toc@l
+; PWR5-NEXT: vsrb 3, 2, 3
+; PWR5-NEXT: lvx 4, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI8_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI8_1 at toc@l
+; PWR5-NEXT: vspltisb 5, 2
+; PWR5-NEXT: vand 3, 3, 4
+; PWR5-NEXT: lvx 4, 0, 3
+; PWR5-NEXT: vsububm 2, 2, 3
+; PWR5-NEXT: vand 3, 2, 4
+; PWR5-NEXT: vsrb 2, 2, 5
+; PWR5-NEXT: vand 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 4
+; PWR5-NEXT: vaddubm 2, 3, 2
+; PWR5-NEXT: vsrb 3, 2, 4
+; PWR5-NEXT: vspltisb 4, 15
+; PWR5-NEXT: vaddubm 2, 2, 3
+; PWR5-NEXT: vspltisb 3, 5
+; PWR5-NEXT: vand 2, 2, 4
+; PWR5-NEXT: vcmpgtub 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_5_v16i8:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI8_0 at toc@ha
+; PWR6-NEXT: vspltisb 3, 1
+; PWR6-NEXT: addi 3, 3, .LCPI8_0 at toc@l
+; PWR6-NEXT: vsrb 3, 2, 3
+; PWR6-NEXT: lvx 4, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI8_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI8_1 at toc@l
+; PWR6-NEXT: vspltisb 5, 2
+; PWR6-NEXT: vand 3, 3, 4
+; PWR6-NEXT: lvx 4, 0, 3
+; PWR6-NEXT: vsububm 2, 2, 3
+; PWR6-NEXT: vand 3, 2, 4
+; PWR6-NEXT: vsrb 2, 2, 5
+; PWR6-NEXT: vand 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 4
+; PWR6-NEXT: vaddubm 2, 3, 2
+; PWR6-NEXT: vsrb 3, 2, 4
+; PWR6-NEXT: vspltisb 4, 15
+; PWR6-NEXT: vaddubm 2, 2, 3
+; PWR6-NEXT: vspltisb 3, 5
+; PWR6-NEXT: vand 2, 2, 4
+; PWR6-NEXT: vcmpgtub 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_5_v16i8:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI8_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI8_0 at toc@l
+; PWR7-NEXT: vspltisb 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI8_1 at toc@ha
+; PWR7-NEXT: vsrb 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI8_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsububm 2, 2, 3
+; PWR7-NEXT: vsrb 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisb 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vaddubm 2, 2, 3
+; PWR7-NEXT: vsrb 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 15
+; PWR7-NEXT: vaddubm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 5
+; PWR7-NEXT: xxland 34, 34, 36
+; PWR7-NEXT: vcmpgtub 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_5_v16i8:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisb 3, 5
+; PWR8-NEXT: vpopcntb 2, 2
+; PWR8-NEXT: vcmpgtub 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_5_v16i8:
+; PWR9: # %bb.0:
+; PWR9-NEXT: xxspltib 35, 5
+; PWR9-NEXT: vpopcntb 2, 2
+; PWR9-NEXT: vcmpgtub 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
+ %3 = icmp ugt <16 x i8> %2, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
+ %4 = sext <16 x i1> %3 to <16 x i8>
+ ret <16 x i8> %4
+}
+
+define <16 x i8> @ult_6_v16i8(<16 x i8> %0) {
+; PWR5-LABEL: ult_6_v16i8:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI9_0 at toc@ha
+; PWR5-NEXT: vspltisb 3, 1
+; PWR5-NEXT: addi 3, 3, .LCPI9_0 at toc@l
+; PWR5-NEXT: vsrb 3, 2, 3
+; PWR5-NEXT: lvx 4, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI9_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI9_1 at toc@l
+; PWR5-NEXT: vspltisb 5, 2
+; PWR5-NEXT: vand 3, 3, 4
+; PWR5-NEXT: lvx 4, 0, 3
+; PWR5-NEXT: vsububm 2, 2, 3
+; PWR5-NEXT: vand 3, 2, 4
+; PWR5-NEXT: vsrb 2, 2, 5
+; PWR5-NEXT: vand 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 4
+; PWR5-NEXT: vaddubm 2, 3, 2
+; PWR5-NEXT: vsrb 3, 2, 4
+; PWR5-NEXT: vspltisb 4, 15
+; PWR5-NEXT: vaddubm 2, 2, 3
+; PWR5-NEXT: vspltisb 3, 6
+; PWR5-NEXT: vand 2, 2, 4
+; PWR5-NEXT: vcmpgtub 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_6_v16i8:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI9_0 at toc@ha
+; PWR6-NEXT: vspltisb 3, 1
+; PWR6-NEXT: addi 3, 3, .LCPI9_0 at toc@l
+; PWR6-NEXT: vsrb 3, 2, 3
+; PWR6-NEXT: lvx 4, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI9_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI9_1 at toc@l
+; PWR6-NEXT: vspltisb 5, 2
+; PWR6-NEXT: vand 3, 3, 4
+; PWR6-NEXT: lvx 4, 0, 3
+; PWR6-NEXT: vsububm 2, 2, 3
+; PWR6-NEXT: vand 3, 2, 4
+; PWR6-NEXT: vsrb 2, 2, 5
+; PWR6-NEXT: vand 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 4
+; PWR6-NEXT: vaddubm 2, 3, 2
+; PWR6-NEXT: vsrb 3, 2, 4
+; PWR6-NEXT: vspltisb 4, 15
+; PWR6-NEXT: vaddubm 2, 2, 3
+; PWR6-NEXT: vspltisb 3, 6
+; PWR6-NEXT: vand 2, 2, 4
+; PWR6-NEXT: vcmpgtub 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_6_v16i8:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI9_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI9_0 at toc@l
+; PWR7-NEXT: vspltisb 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI9_1 at toc@ha
+; PWR7-NEXT: vsrb 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI9_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsububm 2, 2, 3
+; PWR7-NEXT: vsrb 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisb 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vaddubm 2, 2, 3
+; PWR7-NEXT: vsrb 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 15
+; PWR7-NEXT: vaddubm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 6
+; PWR7-NEXT: xxland 34, 34, 36
+; PWR7-NEXT: vcmpgtub 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_6_v16i8:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisb 3, 6
+; PWR8-NEXT: vpopcntb 2, 2
+; PWR8-NEXT: vcmpgtub 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_6_v16i8:
+; PWR9: # %bb.0:
+; PWR9-NEXT: xxspltib 35, 6
+; PWR9-NEXT: vpopcntb 2, 2
+; PWR9-NEXT: vcmpgtub 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
+ %3 = icmp ult <16 x i8> %2, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6>
+ %4 = sext <16 x i1> %3 to <16 x i8>
+ ret <16 x i8> %4
+}
+
+define <16 x i8> @ugt_6_v16i8(<16 x i8> %0) {
+; PWR5-LABEL: ugt_6_v16i8:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI10_0 at toc@ha
+; PWR5-NEXT: vspltisb 3, 1
+; PWR5-NEXT: addi 3, 3, .LCPI10_0 at toc@l
+; PWR5-NEXT: vsrb 3, 2, 3
+; PWR5-NEXT: lvx 4, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI10_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI10_1 at toc@l
+; PWR5-NEXT: vspltisb 5, 2
+; PWR5-NEXT: vand 3, 3, 4
+; PWR5-NEXT: lvx 4, 0, 3
+; PWR5-NEXT: vsububm 2, 2, 3
+; PWR5-NEXT: vand 3, 2, 4
+; PWR5-NEXT: vsrb 2, 2, 5
+; PWR5-NEXT: vand 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 4
+; PWR5-NEXT: vaddubm 2, 3, 2
+; PWR5-NEXT: vsrb 3, 2, 4
+; PWR5-NEXT: vspltisb 4, 15
+; PWR5-NEXT: vaddubm 2, 2, 3
+; PWR5-NEXT: vspltisb 3, 6
+; PWR5-NEXT: vand 2, 2, 4
+; PWR5-NEXT: vcmpgtub 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_6_v16i8:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI10_0 at toc@ha
+; PWR6-NEXT: vspltisb 3, 1
+; PWR6-NEXT: addi 3, 3, .LCPI10_0 at toc@l
+; PWR6-NEXT: vsrb 3, 2, 3
+; PWR6-NEXT: lvx 4, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI10_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI10_1 at toc@l
+; PWR6-NEXT: vspltisb 5, 2
+; PWR6-NEXT: vand 3, 3, 4
+; PWR6-NEXT: lvx 4, 0, 3
+; PWR6-NEXT: vsububm 2, 2, 3
+; PWR6-NEXT: vand 3, 2, 4
+; PWR6-NEXT: vsrb 2, 2, 5
+; PWR6-NEXT: vand 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 4
+; PWR6-NEXT: vaddubm 2, 3, 2
+; PWR6-NEXT: vsrb 3, 2, 4
+; PWR6-NEXT: vspltisb 4, 15
+; PWR6-NEXT: vaddubm 2, 2, 3
+; PWR6-NEXT: vspltisb 3, 6
+; PWR6-NEXT: vand 2, 2, 4
+; PWR6-NEXT: vcmpgtub 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_6_v16i8:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI10_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI10_0 at toc@l
+; PWR7-NEXT: vspltisb 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI10_1 at toc@ha
+; PWR7-NEXT: vsrb 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI10_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsububm 2, 2, 3
+; PWR7-NEXT: vsrb 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisb 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vaddubm 2, 2, 3
+; PWR7-NEXT: vsrb 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 15
+; PWR7-NEXT: vaddubm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 6
+; PWR7-NEXT: xxland 34, 34, 36
+; PWR7-NEXT: vcmpgtub 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_6_v16i8:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisb 3, 6
+; PWR8-NEXT: vpopcntb 2, 2
+; PWR8-NEXT: vcmpgtub 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_6_v16i8:
+; PWR9: # %bb.0:
+; PWR9-NEXT: xxspltib 35, 6
+; PWR9-NEXT: vpopcntb 2, 2
+; PWR9-NEXT: vcmpgtub 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
+ %3 = icmp ugt <16 x i8> %2, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6>
+ %4 = sext <16 x i1> %3 to <16 x i8>
+ ret <16 x i8> %4
+}
+
+define <16 x i8> @ult_7_v16i8(<16 x i8> %0) {
+; PWR5-LABEL: ult_7_v16i8:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI11_0 at toc@ha
+; PWR5-NEXT: vspltisb 3, 1
+; PWR5-NEXT: addi 3, 3, .LCPI11_0 at toc@l
+; PWR5-NEXT: vsrb 3, 2, 3
+; PWR5-NEXT: lvx 4, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI11_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI11_1 at toc@l
+; PWR5-NEXT: vspltisb 5, 2
+; PWR5-NEXT: vand 3, 3, 4
+; PWR5-NEXT: lvx 4, 0, 3
+; PWR5-NEXT: vsububm 2, 2, 3
+; PWR5-NEXT: vand 3, 2, 4
+; PWR5-NEXT: vsrb 2, 2, 5
+; PWR5-NEXT: vand 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 4
+; PWR5-NEXT: vaddubm 2, 3, 2
+; PWR5-NEXT: vsrb 3, 2, 4
+; PWR5-NEXT: vspltisb 4, 15
+; PWR5-NEXT: vaddubm 2, 2, 3
+; PWR5-NEXT: vspltisb 3, 7
+; PWR5-NEXT: vand 2, 2, 4
+; PWR5-NEXT: vcmpgtub 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_7_v16i8:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI11_0 at toc@ha
+; PWR6-NEXT: vspltisb 3, 1
+; PWR6-NEXT: addi 3, 3, .LCPI11_0 at toc@l
+; PWR6-NEXT: vsrb 3, 2, 3
+; PWR6-NEXT: lvx 4, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI11_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI11_1 at toc@l
+; PWR6-NEXT: vspltisb 5, 2
+; PWR6-NEXT: vand 3, 3, 4
+; PWR6-NEXT: lvx 4, 0, 3
+; PWR6-NEXT: vsububm 2, 2, 3
+; PWR6-NEXT: vand 3, 2, 4
+; PWR6-NEXT: vsrb 2, 2, 5
+; PWR6-NEXT: vand 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 4
+; PWR6-NEXT: vaddubm 2, 3, 2
+; PWR6-NEXT: vsrb 3, 2, 4
+; PWR6-NEXT: vspltisb 4, 15
+; PWR6-NEXT: vaddubm 2, 2, 3
+; PWR6-NEXT: vspltisb 3, 7
+; PWR6-NEXT: vand 2, 2, 4
+; PWR6-NEXT: vcmpgtub 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_7_v16i8:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI11_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI11_0 at toc@l
+; PWR7-NEXT: vspltisb 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI11_1 at toc@ha
+; PWR7-NEXT: vsrb 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI11_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsububm 2, 2, 3
+; PWR7-NEXT: vsrb 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisb 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vaddubm 2, 2, 3
+; PWR7-NEXT: vsrb 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 15
+; PWR7-NEXT: vaddubm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 7
+; PWR7-NEXT: xxland 34, 34, 36
+; PWR7-NEXT: vcmpgtub 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_7_v16i8:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisb 3, 7
+; PWR8-NEXT: vpopcntb 2, 2
+; PWR8-NEXT: vcmpgtub 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_7_v16i8:
+; PWR9: # %bb.0:
+; PWR9-NEXT: xxspltib 35, 7
+; PWR9-NEXT: vpopcntb 2, 2
+; PWR9-NEXT: vcmpgtub 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
+ %3 = icmp ult <16 x i8> %2, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
+ %4 = sext <16 x i1> %3 to <16 x i8>
+ ret <16 x i8> %4
+}
+
+define <8 x i16> @ugt_1_v8i16(<8 x i16> %0) {
+; PWR5-LABEL: ugt_1_v8i16:
+; PWR5: # %bb.0:
+; PWR5-NEXT: vspltisb 3, -1
+; PWR5-NEXT: vadduhm 3, 2, 3
+; PWR5-NEXT: vand 2, 2, 3
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: vcmpequh 2, 2, 3
+; PWR5-NEXT: vnot 2, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_1_v8i16:
+; PWR6: # %bb.0:
+; PWR6-NEXT: vspltisb 3, -1
+; PWR6-NEXT: vadduhm 3, 2, 3
+; PWR6-NEXT: vand 2, 2, 3
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: vcmpequh 2, 2, 3
+; PWR6-NEXT: vnot 2, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_1_v8i16:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisb 3, -1
+; PWR7-NEXT: vadduhm 3, 2, 3
+; PWR7-NEXT: xxland 34, 34, 35
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: vcmpequh 2, 2, 3
+; PWR7-NEXT: xxlnor 34, 34, 34
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_1_v8i16:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltish 3, 1
+; PWR8-NEXT: vpopcnth 2, 2
+; PWR8-NEXT: vcmpgtuh 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_1_v8i16:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltish 3, 1
+; PWR9-NEXT: vpopcnth 2, 2
+; PWR9-NEXT: vcmpgtuh 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ugt <8 x i16> %2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ult_2_v8i16(<8 x i16> %0) {
+; PWR5-LABEL: ult_2_v8i16:
+; PWR5: # %bb.0:
+; PWR5-NEXT: vspltisb 3, -1
+; PWR5-NEXT: vadduhm 3, 2, 3
+; PWR5-NEXT: vand 2, 2, 3
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: vcmpequh 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_2_v8i16:
+; PWR6: # %bb.0:
+; PWR6-NEXT: vspltisb 3, -1
+; PWR6-NEXT: vadduhm 3, 2, 3
+; PWR6-NEXT: vand 2, 2, 3
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: vcmpequh 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_2_v8i16:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisb 3, -1
+; PWR7-NEXT: vadduhm 3, 2, 3
+; PWR7-NEXT: xxland 34, 34, 35
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: vcmpequh 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_2_v8i16:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltish 3, 2
+; PWR8-NEXT: vpopcnth 2, 2
+; PWR8-NEXT: vcmpgtuh 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_2_v8i16:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltish 3, 2
+; PWR9-NEXT: vpopcnth 2, 2
+; PWR9-NEXT: vcmpgtuh 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ult <8 x i16> %2, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ugt_2_v8i16(<8 x i16> %0) {
+; PWR5-LABEL: ugt_2_v8i16:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI14_0 at toc@ha
+; PWR5-NEXT: vspltish 3, 1
+; PWR5-NEXT: addi 3, 3, .LCPI14_0 at toc@l
+; PWR5-NEXT: vsrh 3, 2, 3
+; PWR5-NEXT: lvx 4, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI14_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI14_1 at toc@l
+; PWR5-NEXT: vspltish 5, 2
+; PWR5-NEXT: vand 3, 3, 4
+; PWR5-NEXT: lvx 4, 0, 3
+; PWR5-NEXT: vsubuhm 2, 2, 3
+; PWR5-NEXT: vand 3, 2, 4
+; PWR5-NEXT: vsrh 2, 2, 5
+; PWR5-NEXT: vand 2, 2, 4
+; PWR5-NEXT: vadduhm 2, 3, 2
+; PWR5-NEXT: vspltish 3, 4
+; PWR5-NEXT: vsrh 3, 2, 3
+; PWR5-NEXT: vadduhm 2, 2, 3
+; PWR5-NEXT: vspltisb 3, 15
+; PWR5-NEXT: vxor 4, 4, 4
+; PWR5-NEXT: vand 2, 2, 3
+; PWR5-NEXT: vspltisb 3, 1
+; PWR5-NEXT: vmladduhm 2, 2, 3, 4
+; PWR5-NEXT: vspltish 3, 8
+; PWR5-NEXT: vsrh 2, 2, 3
+; PWR5-NEXT: vcmpgtuh 2, 2, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_2_v8i16:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI14_0 at toc@ha
+; PWR6-NEXT: vspltish 3, 1
+; PWR6-NEXT: addi 3, 3, .LCPI14_0 at toc@l
+; PWR6-NEXT: vsrh 3, 2, 3
+; PWR6-NEXT: lvx 4, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI14_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI14_1 at toc@l
+; PWR6-NEXT: vspltish 5, 2
+; PWR6-NEXT: vand 3, 3, 4
+; PWR6-NEXT: lvx 4, 0, 3
+; PWR6-NEXT: vsubuhm 2, 2, 3
+; PWR6-NEXT: vand 3, 2, 4
+; PWR6-NEXT: vsrh 2, 2, 5
+; PWR6-NEXT: vand 2, 2, 4
+; PWR6-NEXT: vadduhm 2, 3, 2
+; PWR6-NEXT: vspltish 3, 4
+; PWR6-NEXT: vsrh 3, 2, 3
+; PWR6-NEXT: vadduhm 2, 2, 3
+; PWR6-NEXT: vspltisb 3, 15
+; PWR6-NEXT: vxor 4, 4, 4
+; PWR6-NEXT: vand 2, 2, 3
+; PWR6-NEXT: vspltisb 3, 1
+; PWR6-NEXT: vmladduhm 2, 2, 3, 4
+; PWR6-NEXT: vspltish 3, 8
+; PWR6-NEXT: vsrh 2, 2, 3
+; PWR6-NEXT: vcmpgtuh 2, 2, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_2_v8i16:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltish 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI14_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI14_0 at toc@l
+; PWR7-NEXT: vspltish 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI14_1 at toc@ha
+; PWR7-NEXT: vspltish 5, 4
+; PWR7-NEXT: vsrh 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI14_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 5
+; PWR7-NEXT: vxor 5, 5, 5
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmladduhm 2, 2, 3, 5
+; PWR7-NEXT: vspltish 3, 8
+; PWR7-NEXT: vsrh 2, 2, 3
+; PWR7-NEXT: vcmpgtuh 2, 2, 4
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_2_v8i16:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltish 3, 2
+; PWR8-NEXT: vpopcnth 2, 2
+; PWR8-NEXT: vcmpgtuh 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_2_v8i16:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltish 3, 2
+; PWR9-NEXT: vpopcnth 2, 2
+; PWR9-NEXT: vcmpgtuh 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ugt <8 x i16> %2, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ult_3_v8i16(<8 x i16> %0) {
+; PWR5-LABEL: ult_3_v8i16:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI15_0 at toc@ha
+; PWR5-NEXT: vspltish 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI15_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI15_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI15_1 at toc@l
+; PWR5-NEXT: vsrh 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 2
+; PWR5-NEXT: vsubuhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 4
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vmladduhm 2, 2, 4, 3
+; PWR5-NEXT: vspltish 3, 8
+; PWR5-NEXT: vsrh 2, 2, 3
+; PWR5-NEXT: vspltish 3, 3
+; PWR5-NEXT: vcmpgtuh 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_3_v8i16:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI15_0 at toc@ha
+; PWR6-NEXT: vspltish 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI15_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI15_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI15_1 at toc@l
+; PWR6-NEXT: vsrh 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 2
+; PWR6-NEXT: vsubuhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 4
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vmladduhm 2, 2, 4, 3
+; PWR6-NEXT: vspltish 3, 8
+; PWR6-NEXT: vsrh 2, 2, 3
+; PWR6-NEXT: vspltish 3, 3
+; PWR6-NEXT: vcmpgtuh 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_3_v8i16:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltish 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI15_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI15_0 at toc@l
+; PWR7-NEXT: vspltish 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI15_1 at toc@ha
+; PWR7-NEXT: vspltisb 5, 15
+; PWR7-NEXT: vsrh 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI15_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltish 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: vxor 4, 4, 4
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: xxland 34, 34, 37
+; PWR7-NEXT: vmladduhm 2, 2, 3, 4
+; PWR7-NEXT: vspltish 3, 8
+; PWR7-NEXT: vsrh 2, 2, 3
+; PWR7-NEXT: vspltish 3, 3
+; PWR7-NEXT: vcmpgtuh 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_3_v8i16:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltish 3, 3
+; PWR8-NEXT: vpopcnth 2, 2
+; PWR8-NEXT: vcmpgtuh 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_3_v8i16:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltish 3, 3
+; PWR9-NEXT: vpopcnth 2, 2
+; PWR9-NEXT: vcmpgtuh 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ult <8 x i16> %2, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ugt_3_v8i16(<8 x i16> %0) {
+; PWR5-LABEL: ugt_3_v8i16:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI16_0 at toc@ha
+; PWR5-NEXT: vspltish 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI16_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI16_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI16_1 at toc@l
+; PWR5-NEXT: vsrh 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 2
+; PWR5-NEXT: vsubuhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 4
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vmladduhm 2, 2, 4, 3
+; PWR5-NEXT: vspltish 3, 8
+; PWR5-NEXT: vsrh 2, 2, 3
+; PWR5-NEXT: vspltish 3, 3
+; PWR5-NEXT: vcmpgtuh 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_3_v8i16:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI16_0 at toc@ha
+; PWR6-NEXT: vspltish 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI16_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI16_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI16_1 at toc@l
+; PWR6-NEXT: vsrh 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 2
+; PWR6-NEXT: vsubuhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 4
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vmladduhm 2, 2, 4, 3
+; PWR6-NEXT: vspltish 3, 8
+; PWR6-NEXT: vsrh 2, 2, 3
+; PWR6-NEXT: vspltish 3, 3
+; PWR6-NEXT: vcmpgtuh 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_3_v8i16:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltish 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI16_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI16_0 at toc@l
+; PWR7-NEXT: vspltish 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI16_1 at toc@ha
+; PWR7-NEXT: vspltisb 5, 15
+; PWR7-NEXT: vsrh 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI16_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltish 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: vxor 4, 4, 4
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: xxland 34, 34, 37
+; PWR7-NEXT: vmladduhm 2, 2, 3, 4
+; PWR7-NEXT: vspltish 3, 8
+; PWR7-NEXT: vsrh 2, 2, 3
+; PWR7-NEXT: vspltish 3, 3
+; PWR7-NEXT: vcmpgtuh 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_3_v8i16:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltish 3, 3
+; PWR8-NEXT: vpopcnth 2, 2
+; PWR8-NEXT: vcmpgtuh 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_3_v8i16:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltish 3, 3
+; PWR9-NEXT: vpopcnth 2, 2
+; PWR9-NEXT: vcmpgtuh 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ugt <8 x i16> %2, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ult_4_v8i16(<8 x i16> %0) {
+; PWR5-LABEL: ult_4_v8i16:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI17_0 at toc@ha
+; PWR5-NEXT: vspltish 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI17_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI17_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI17_1 at toc@l
+; PWR5-NEXT: vsrh 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 2
+; PWR5-NEXT: vsubuhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 4
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 15
+; PWR5-NEXT: vand 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vmladduhm 2, 2, 4, 3
+; PWR5-NEXT: vspltish 3, 8
+; PWR5-NEXT: vsrh 2, 2, 3
+; PWR5-NEXT: vcmpgtuh 2, 5, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_4_v8i16:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI17_0 at toc@ha
+; PWR6-NEXT: vspltish 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI17_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI17_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI17_1 at toc@l
+; PWR6-NEXT: vsrh 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 2
+; PWR6-NEXT: vsubuhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 4
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 15
+; PWR6-NEXT: vand 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vmladduhm 2, 2, 4, 3
+; PWR6-NEXT: vspltish 3, 8
+; PWR6-NEXT: vsrh 2, 2, 3
+; PWR6-NEXT: vcmpgtuh 2, 5, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_4_v8i16:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltish 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI17_0 at toc@ha
+; PWR7-NEXT: vxor 5, 5, 5
+; PWR7-NEXT: addi 3, 3, .LCPI17_0 at toc@l
+; PWR7-NEXT: vspltish 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI17_1 at toc@ha
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: vsrh 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI17_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltish 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmladduhm 2, 2, 3, 5
+; PWR7-NEXT: vspltish 3, 8
+; PWR7-NEXT: vsrh 2, 2, 3
+; PWR7-NEXT: vcmpgtuh 2, 4, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_4_v8i16:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltish 3, 4
+; PWR8-NEXT: vpopcnth 2, 2
+; PWR8-NEXT: vcmpgtuh 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_4_v8i16:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltish 3, 4
+; PWR9-NEXT: vpopcnth 2, 2
+; PWR9-NEXT: vcmpgtuh 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ult <8 x i16> %2, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ugt_4_v8i16(<8 x i16> %0) {
+; PWR5-LABEL: ugt_4_v8i16:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI18_0 at toc@ha
+; PWR5-NEXT: vspltish 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI18_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI18_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI18_1 at toc@l
+; PWR5-NEXT: vsrh 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 2
+; PWR5-NEXT: vsubuhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 4
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 15
+; PWR5-NEXT: vand 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vmladduhm 2, 2, 4, 3
+; PWR5-NEXT: vspltish 3, 8
+; PWR5-NEXT: vsrh 2, 2, 3
+; PWR5-NEXT: vcmpgtuh 2, 2, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_4_v8i16:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI18_0 at toc@ha
+; PWR6-NEXT: vspltish 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI18_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI18_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI18_1 at toc@l
+; PWR6-NEXT: vsrh 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 2
+; PWR6-NEXT: vsubuhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 4
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 15
+; PWR6-NEXT: vand 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vmladduhm 2, 2, 4, 3
+; PWR6-NEXT: vspltish 3, 8
+; PWR6-NEXT: vsrh 2, 2, 3
+; PWR6-NEXT: vcmpgtuh 2, 2, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_4_v8i16:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltish 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI18_0 at toc@ha
+; PWR7-NEXT: vxor 5, 5, 5
+; PWR7-NEXT: addi 3, 3, .LCPI18_0 at toc@l
+; PWR7-NEXT: vspltish 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI18_1 at toc@ha
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: vsrh 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI18_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltish 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmladduhm 2, 2, 3, 5
+; PWR7-NEXT: vspltish 3, 8
+; PWR7-NEXT: vsrh 2, 2, 3
+; PWR7-NEXT: vcmpgtuh 2, 2, 4
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_4_v8i16:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltish 3, 4
+; PWR8-NEXT: vpopcnth 2, 2
+; PWR8-NEXT: vcmpgtuh 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_4_v8i16:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltish 3, 4
+; PWR9-NEXT: vpopcnth 2, 2
+; PWR9-NEXT: vcmpgtuh 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ugt <8 x i16> %2, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ult_5_v8i16(<8 x i16> %0) {
+; PWR5-LABEL: ult_5_v8i16:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI19_0 at toc@ha
+; PWR5-NEXT: vspltish 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI19_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI19_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI19_1 at toc@l
+; PWR5-NEXT: vsrh 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 2
+; PWR5-NEXT: vsubuhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 4
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vmladduhm 2, 2, 4, 3
+; PWR5-NEXT: vspltish 3, 8
+; PWR5-NEXT: vsrh 2, 2, 3
+; PWR5-NEXT: vspltish 3, 5
+; PWR5-NEXT: vcmpgtuh 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_5_v8i16:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI19_0 at toc@ha
+; PWR6-NEXT: vspltish 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI19_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI19_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI19_1 at toc@l
+; PWR6-NEXT: vsrh 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 2
+; PWR6-NEXT: vsubuhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 4
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vmladduhm 2, 2, 4, 3
+; PWR6-NEXT: vspltish 3, 8
+; PWR6-NEXT: vsrh 2, 2, 3
+; PWR6-NEXT: vspltish 3, 5
+; PWR6-NEXT: vcmpgtuh 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_5_v8i16:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltish 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI19_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI19_0 at toc@l
+; PWR7-NEXT: vspltish 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI19_1 at toc@ha
+; PWR7-NEXT: vspltisb 5, 15
+; PWR7-NEXT: vsrh 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI19_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltish 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: vxor 4, 4, 4
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: xxland 34, 34, 37
+; PWR7-NEXT: vmladduhm 2, 2, 3, 4
+; PWR7-NEXT: vspltish 3, 8
+; PWR7-NEXT: vsrh 2, 2, 3
+; PWR7-NEXT: vspltish 3, 5
+; PWR7-NEXT: vcmpgtuh 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_5_v8i16:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltish 3, 5
+; PWR8-NEXT: vpopcnth 2, 2
+; PWR8-NEXT: vcmpgtuh 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_5_v8i16:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltish 3, 5
+; PWR9-NEXT: vpopcnth 2, 2
+; PWR9-NEXT: vcmpgtuh 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ult <8 x i16> %2, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ugt_5_v8i16(<8 x i16> %0) {
+; PWR5-LABEL: ugt_5_v8i16:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI20_0 at toc@ha
+; PWR5-NEXT: vspltish 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI20_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI20_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI20_1 at toc@l
+; PWR5-NEXT: vsrh 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 2
+; PWR5-NEXT: vsubuhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 4
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vmladduhm 2, 2, 4, 3
+; PWR5-NEXT: vspltish 3, 8
+; PWR5-NEXT: vsrh 2, 2, 3
+; PWR5-NEXT: vspltish 3, 5
+; PWR5-NEXT: vcmpgtuh 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_5_v8i16:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI20_0 at toc@ha
+; PWR6-NEXT: vspltish 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI20_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI20_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI20_1 at toc@l
+; PWR6-NEXT: vsrh 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 2
+; PWR6-NEXT: vsubuhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 4
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vmladduhm 2, 2, 4, 3
+; PWR6-NEXT: vspltish 3, 8
+; PWR6-NEXT: vsrh 2, 2, 3
+; PWR6-NEXT: vspltish 3, 5
+; PWR6-NEXT: vcmpgtuh 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_5_v8i16:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltish 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI20_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI20_0 at toc@l
+; PWR7-NEXT: vspltish 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI20_1 at toc@ha
+; PWR7-NEXT: vspltisb 5, 15
+; PWR7-NEXT: vsrh 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI20_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltish 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: vxor 4, 4, 4
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: xxland 34, 34, 37
+; PWR7-NEXT: vmladduhm 2, 2, 3, 4
+; PWR7-NEXT: vspltish 3, 8
+; PWR7-NEXT: vsrh 2, 2, 3
+; PWR7-NEXT: vspltish 3, 5
+; PWR7-NEXT: vcmpgtuh 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_5_v8i16:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltish 3, 5
+; PWR8-NEXT: vpopcnth 2, 2
+; PWR8-NEXT: vcmpgtuh 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_5_v8i16:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltish 3, 5
+; PWR9-NEXT: vpopcnth 2, 2
+; PWR9-NEXT: vcmpgtuh 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ugt <8 x i16> %2, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ult_6_v8i16(<8 x i16> %0) {
+; PWR5-LABEL: ult_6_v8i16:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI21_0 at toc@ha
+; PWR5-NEXT: vspltish 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI21_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI21_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI21_1 at toc@l
+; PWR5-NEXT: vsrh 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 2
+; PWR5-NEXT: vsubuhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 4
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vmladduhm 2, 2, 4, 3
+; PWR5-NEXT: vspltish 3, 8
+; PWR5-NEXT: vsrh 2, 2, 3
+; PWR5-NEXT: vspltish 3, 6
+; PWR5-NEXT: vcmpgtuh 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_6_v8i16:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI21_0 at toc@ha
+; PWR6-NEXT: vspltish 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI21_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI21_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI21_1 at toc@l
+; PWR6-NEXT: vsrh 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 2
+; PWR6-NEXT: vsubuhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 4
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vmladduhm 2, 2, 4, 3
+; PWR6-NEXT: vspltish 3, 8
+; PWR6-NEXT: vsrh 2, 2, 3
+; PWR6-NEXT: vspltish 3, 6
+; PWR6-NEXT: vcmpgtuh 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_6_v8i16:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltish 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI21_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI21_0 at toc@l
+; PWR7-NEXT: vspltish 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI21_1 at toc@ha
+; PWR7-NEXT: vspltisb 5, 15
+; PWR7-NEXT: vsrh 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI21_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltish 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: vxor 4, 4, 4
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: xxland 34, 34, 37
+; PWR7-NEXT: vmladduhm 2, 2, 3, 4
+; PWR7-NEXT: vspltish 3, 8
+; PWR7-NEXT: vsrh 2, 2, 3
+; PWR7-NEXT: vspltish 3, 6
+; PWR7-NEXT: vcmpgtuh 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_6_v8i16:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltish 3, 6
+; PWR8-NEXT: vpopcnth 2, 2
+; PWR8-NEXT: vcmpgtuh 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_6_v8i16:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltish 3, 6
+; PWR9-NEXT: vpopcnth 2, 2
+; PWR9-NEXT: vcmpgtuh 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ult <8 x i16> %2, <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ugt_6_v8i16(<8 x i16> %0) {
+; PWR5-LABEL: ugt_6_v8i16:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI22_0 at toc@ha
+; PWR5-NEXT: vspltish 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI22_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI22_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI22_1 at toc@l
+; PWR5-NEXT: vsrh 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 2
+; PWR5-NEXT: vsubuhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 4
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vmladduhm 2, 2, 4, 3
+; PWR5-NEXT: vspltish 3, 8
+; PWR5-NEXT: vsrh 2, 2, 3
+; PWR5-NEXT: vspltish 3, 6
+; PWR5-NEXT: vcmpgtuh 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_6_v8i16:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI22_0 at toc@ha
+; PWR6-NEXT: vspltish 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI22_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI22_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI22_1 at toc@l
+; PWR6-NEXT: vsrh 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 2
+; PWR6-NEXT: vsubuhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 4
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vmladduhm 2, 2, 4, 3
+; PWR6-NEXT: vspltish 3, 8
+; PWR6-NEXT: vsrh 2, 2, 3
+; PWR6-NEXT: vspltish 3, 6
+; PWR6-NEXT: vcmpgtuh 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_6_v8i16:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltish 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI22_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI22_0 at toc@l
+; PWR7-NEXT: vspltish 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI22_1 at toc@ha
+; PWR7-NEXT: vspltisb 5, 15
+; PWR7-NEXT: vsrh 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI22_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltish 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: vxor 4, 4, 4
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: xxland 34, 34, 37
+; PWR7-NEXT: vmladduhm 2, 2, 3, 4
+; PWR7-NEXT: vspltish 3, 8
+; PWR7-NEXT: vsrh 2, 2, 3
+; PWR7-NEXT: vspltish 3, 6
+; PWR7-NEXT: vcmpgtuh 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_6_v8i16:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltish 3, 6
+; PWR8-NEXT: vpopcnth 2, 2
+; PWR8-NEXT: vcmpgtuh 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_6_v8i16:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltish 3, 6
+; PWR9-NEXT: vpopcnth 2, 2
+; PWR9-NEXT: vcmpgtuh 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ugt <8 x i16> %2, <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ult_7_v8i16(<8 x i16> %0) {
+; PWR5-LABEL: ult_7_v8i16:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI23_0 at toc@ha
+; PWR5-NEXT: vspltish 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI23_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI23_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI23_1 at toc@l
+; PWR5-NEXT: vsrh 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 2
+; PWR5-NEXT: vsubuhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 4
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vmladduhm 2, 2, 4, 3
+; PWR5-NEXT: vspltish 3, 8
+; PWR5-NEXT: vsrh 2, 2, 3
+; PWR5-NEXT: vspltish 3, 7
+; PWR5-NEXT: vcmpgtuh 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_7_v8i16:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI23_0 at toc@ha
+; PWR6-NEXT: vspltish 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI23_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI23_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI23_1 at toc@l
+; PWR6-NEXT: vsrh 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 2
+; PWR6-NEXT: vsubuhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 4
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vmladduhm 2, 2, 4, 3
+; PWR6-NEXT: vspltish 3, 8
+; PWR6-NEXT: vsrh 2, 2, 3
+; PWR6-NEXT: vspltish 3, 7
+; PWR6-NEXT: vcmpgtuh 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_7_v8i16:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltish 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI23_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI23_0 at toc@l
+; PWR7-NEXT: vspltish 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI23_1 at toc@ha
+; PWR7-NEXT: vspltisb 5, 15
+; PWR7-NEXT: vsrh 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI23_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltish 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: vxor 4, 4, 4
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: xxland 34, 34, 37
+; PWR7-NEXT: vmladduhm 2, 2, 3, 4
+; PWR7-NEXT: vspltish 3, 8
+; PWR7-NEXT: vsrh 2, 2, 3
+; PWR7-NEXT: vspltish 3, 7
+; PWR7-NEXT: vcmpgtuh 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_7_v8i16:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltish 3, 7
+; PWR8-NEXT: vpopcnth 2, 2
+; PWR8-NEXT: vcmpgtuh 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_7_v8i16:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltish 3, 7
+; PWR9-NEXT: vpopcnth 2, 2
+; PWR9-NEXT: vcmpgtuh 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ult <8 x i16> %2, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ugt_7_v8i16(<8 x i16> %0) {
+; PWR5-LABEL: ugt_7_v8i16:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI24_0 at toc@ha
+; PWR5-NEXT: vspltish 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI24_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI24_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI24_1 at toc@l
+; PWR5-NEXT: vsrh 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 2
+; PWR5-NEXT: vsubuhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 4
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vmladduhm 2, 2, 4, 3
+; PWR5-NEXT: vspltish 3, 8
+; PWR5-NEXT: vsrh 2, 2, 3
+; PWR5-NEXT: vspltish 3, 7
+; PWR5-NEXT: vcmpgtuh 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_7_v8i16:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI24_0 at toc@ha
+; PWR6-NEXT: vspltish 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI24_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI24_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI24_1 at toc@l
+; PWR6-NEXT: vsrh 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 2
+; PWR6-NEXT: vsubuhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 4
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vmladduhm 2, 2, 4, 3
+; PWR6-NEXT: vspltish 3, 8
+; PWR6-NEXT: vsrh 2, 2, 3
+; PWR6-NEXT: vspltish 3, 7
+; PWR6-NEXT: vcmpgtuh 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_7_v8i16:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltish 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI24_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI24_0 at toc@l
+; PWR7-NEXT: vspltish 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI24_1 at toc@ha
+; PWR7-NEXT: vspltisb 5, 15
+; PWR7-NEXT: vsrh 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI24_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltish 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: vxor 4, 4, 4
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: xxland 34, 34, 37
+; PWR7-NEXT: vmladduhm 2, 2, 3, 4
+; PWR7-NEXT: vspltish 3, 8
+; PWR7-NEXT: vsrh 2, 2, 3
+; PWR7-NEXT: vspltish 3, 7
+; PWR7-NEXT: vcmpgtuh 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_7_v8i16:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltish 3, 7
+; PWR8-NEXT: vpopcnth 2, 2
+; PWR8-NEXT: vcmpgtuh 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_7_v8i16:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltish 3, 7
+; PWR9-NEXT: vpopcnth 2, 2
+; PWR9-NEXT: vcmpgtuh 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ugt <8 x i16> %2, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ult_8_v8i16(<8 x i16> %0) {
+; PWR5-LABEL: ult_8_v8i16:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI25_0 at toc@ha
+; PWR5-NEXT: vspltish 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI25_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI25_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI25_1 at toc@l
+; PWR5-NEXT: vsrh 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 2
+; PWR5-NEXT: vsubuhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 4
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vmladduhm 2, 2, 4, 3
+; PWR5-NEXT: vspltish 3, 8
+; PWR5-NEXT: vsrh 2, 2, 3
+; PWR5-NEXT: vcmpgtuh 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_8_v8i16:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI25_0 at toc@ha
+; PWR6-NEXT: vspltish 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI25_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI25_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI25_1 at toc@l
+; PWR6-NEXT: vsrh 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 2
+; PWR6-NEXT: vsubuhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 4
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vmladduhm 2, 2, 4, 3
+; PWR6-NEXT: vspltish 3, 8
+; PWR6-NEXT: vsrh 2, 2, 3
+; PWR6-NEXT: vcmpgtuh 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_8_v8i16:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltish 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI25_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI25_0 at toc@l
+; PWR7-NEXT: vspltish 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI25_1 at toc@ha
+; PWR7-NEXT: vspltisb 5, 15
+; PWR7-NEXT: vsrh 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI25_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltish 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: vxor 4, 4, 4
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: xxland 34, 34, 37
+; PWR7-NEXT: vmladduhm 2, 2, 3, 4
+; PWR7-NEXT: vspltish 3, 8
+; PWR7-NEXT: vsrh 2, 2, 3
+; PWR7-NEXT: vcmpgtuh 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_8_v8i16:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltish 3, 8
+; PWR8-NEXT: vpopcnth 2, 2
+; PWR8-NEXT: vcmpgtuh 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_8_v8i16:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltish 3, 8
+; PWR9-NEXT: vpopcnth 2, 2
+; PWR9-NEXT: vcmpgtuh 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ult <8 x i16> %2, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ugt_8_v8i16(<8 x i16> %0) {
+; PWR5-LABEL: ugt_8_v8i16:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI26_0 at toc@ha
+; PWR5-NEXT: vspltish 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI26_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI26_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI26_1 at toc@l
+; PWR5-NEXT: vsrh 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 2
+; PWR5-NEXT: vsubuhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 4
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vmladduhm 2, 2, 4, 3
+; PWR5-NEXT: vspltish 3, 8
+; PWR5-NEXT: vsrh 2, 2, 3
+; PWR5-NEXT: vcmpgtuh 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_8_v8i16:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI26_0 at toc@ha
+; PWR6-NEXT: vspltish 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI26_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI26_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI26_1 at toc@l
+; PWR6-NEXT: vsrh 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 2
+; PWR6-NEXT: vsubuhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 4
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vmladduhm 2, 2, 4, 3
+; PWR6-NEXT: vspltish 3, 8
+; PWR6-NEXT: vsrh 2, 2, 3
+; PWR6-NEXT: vcmpgtuh 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_8_v8i16:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltish 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI26_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI26_0 at toc@l
+; PWR7-NEXT: vspltish 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI26_1 at toc@ha
+; PWR7-NEXT: vspltisb 5, 15
+; PWR7-NEXT: vsrh 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI26_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltish 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: vxor 4, 4, 4
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: xxland 34, 34, 37
+; PWR7-NEXT: vmladduhm 2, 2, 3, 4
+; PWR7-NEXT: vspltish 3, 8
+; PWR7-NEXT: vsrh 2, 2, 3
+; PWR7-NEXT: vcmpgtuh 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_8_v8i16:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltish 3, 8
+; PWR8-NEXT: vpopcnth 2, 2
+; PWR8-NEXT: vcmpgtuh 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_8_v8i16:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltish 3, 8
+; PWR9-NEXT: vpopcnth 2, 2
+; PWR9-NEXT: vcmpgtuh 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ugt <8 x i16> %2, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ult_9_v8i16(<8 x i16> %0) {
+; PWR5-LABEL: ult_9_v8i16:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI27_0 at toc@ha
+; PWR5-NEXT: vspltish 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI27_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI27_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI27_1 at toc@l
+; PWR5-NEXT: vsrh 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 2
+; PWR5-NEXT: vsubuhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 4
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vmladduhm 2, 2, 4, 3
+; PWR5-NEXT: vspltish 3, 8
+; PWR5-NEXT: vsrh 2, 2, 3
+; PWR5-NEXT: vspltish 3, 9
+; PWR5-NEXT: vcmpgtuh 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_9_v8i16:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI27_0 at toc@ha
+; PWR6-NEXT: vspltish 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI27_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI27_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI27_1 at toc@l
+; PWR6-NEXT: vsrh 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 2
+; PWR6-NEXT: vsubuhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 4
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vmladduhm 2, 2, 4, 3
+; PWR6-NEXT: vspltish 3, 8
+; PWR6-NEXT: vsrh 2, 2, 3
+; PWR6-NEXT: vspltish 3, 9
+; PWR6-NEXT: vcmpgtuh 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_9_v8i16:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltish 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI27_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI27_0 at toc@l
+; PWR7-NEXT: vspltish 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI27_1 at toc@ha
+; PWR7-NEXT: vspltisb 5, 15
+; PWR7-NEXT: vsrh 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI27_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltish 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: vxor 4, 4, 4
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: xxland 34, 34, 37
+; PWR7-NEXT: vmladduhm 2, 2, 3, 4
+; PWR7-NEXT: vspltish 3, 8
+; PWR7-NEXT: vsrh 2, 2, 3
+; PWR7-NEXT: vspltish 3, 9
+; PWR7-NEXT: vcmpgtuh 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_9_v8i16:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltish 3, 9
+; PWR8-NEXT: vpopcnth 2, 2
+; PWR8-NEXT: vcmpgtuh 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_9_v8i16:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltish 3, 9
+; PWR9-NEXT: vpopcnth 2, 2
+; PWR9-NEXT: vcmpgtuh 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ult <8 x i16> %2, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ugt_9_v8i16(<8 x i16> %0) {
+; PWR5-LABEL: ugt_9_v8i16:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI28_0 at toc@ha
+; PWR5-NEXT: vspltish 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI28_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI28_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI28_1 at toc@l
+; PWR5-NEXT: vsrh 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 2
+; PWR5-NEXT: vsubuhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 4
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vmladduhm 2, 2, 4, 3
+; PWR5-NEXT: vspltish 3, 8
+; PWR5-NEXT: vsrh 2, 2, 3
+; PWR5-NEXT: vspltish 3, 9
+; PWR5-NEXT: vcmpgtuh 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_9_v8i16:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI28_0 at toc@ha
+; PWR6-NEXT: vspltish 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI28_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI28_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI28_1 at toc@l
+; PWR6-NEXT: vsrh 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 2
+; PWR6-NEXT: vsubuhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 4
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vmladduhm 2, 2, 4, 3
+; PWR6-NEXT: vspltish 3, 8
+; PWR6-NEXT: vsrh 2, 2, 3
+; PWR6-NEXT: vspltish 3, 9
+; PWR6-NEXT: vcmpgtuh 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_9_v8i16:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltish 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI28_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI28_0 at toc@l
+; PWR7-NEXT: vspltish 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI28_1 at toc@ha
+; PWR7-NEXT: vspltisb 5, 15
+; PWR7-NEXT: vsrh 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI28_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltish 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: vxor 4, 4, 4
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: xxland 34, 34, 37
+; PWR7-NEXT: vmladduhm 2, 2, 3, 4
+; PWR7-NEXT: vspltish 3, 8
+; PWR7-NEXT: vsrh 2, 2, 3
+; PWR7-NEXT: vspltish 3, 9
+; PWR7-NEXT: vcmpgtuh 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_9_v8i16:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltish 3, 9
+; PWR8-NEXT: vpopcnth 2, 2
+; PWR8-NEXT: vcmpgtuh 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_9_v8i16:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltish 3, 9
+; PWR9-NEXT: vpopcnth 2, 2
+; PWR9-NEXT: vcmpgtuh 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ugt <8 x i16> %2, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ult_10_v8i16(<8 x i16> %0) {
+; PWR5-LABEL: ult_10_v8i16:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI29_0 at toc@ha
+; PWR5-NEXT: vspltish 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI29_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI29_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI29_1 at toc@l
+; PWR5-NEXT: vsrh 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 2
+; PWR5-NEXT: vsubuhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 4
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vmladduhm 2, 2, 4, 3
+; PWR5-NEXT: vspltish 3, 8
+; PWR5-NEXT: vsrh 2, 2, 3
+; PWR5-NEXT: vspltish 3, 10
+; PWR5-NEXT: vcmpgtuh 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_10_v8i16:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI29_0 at toc@ha
+; PWR6-NEXT: vspltish 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI29_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI29_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI29_1 at toc@l
+; PWR6-NEXT: vsrh 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 2
+; PWR6-NEXT: vsubuhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 4
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vmladduhm 2, 2, 4, 3
+; PWR6-NEXT: vspltish 3, 8
+; PWR6-NEXT: vsrh 2, 2, 3
+; PWR6-NEXT: vspltish 3, 10
+; PWR6-NEXT: vcmpgtuh 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_10_v8i16:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltish 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI29_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI29_0 at toc@l
+; PWR7-NEXT: vspltish 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI29_1 at toc@ha
+; PWR7-NEXT: vspltisb 5, 15
+; PWR7-NEXT: vsrh 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI29_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltish 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: vxor 4, 4, 4
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: xxland 34, 34, 37
+; PWR7-NEXT: vmladduhm 2, 2, 3, 4
+; PWR7-NEXT: vspltish 3, 8
+; PWR7-NEXT: vsrh 2, 2, 3
+; PWR7-NEXT: vspltish 3, 10
+; PWR7-NEXT: vcmpgtuh 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_10_v8i16:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltish 3, 10
+; PWR8-NEXT: vpopcnth 2, 2
+; PWR8-NEXT: vcmpgtuh 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_10_v8i16:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltish 3, 10
+; PWR9-NEXT: vpopcnth 2, 2
+; PWR9-NEXT: vcmpgtuh 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ult <8 x i16> %2, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ugt_10_v8i16(<8 x i16> %0) {
+; PWR5-LABEL: ugt_10_v8i16:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI30_0 at toc@ha
+; PWR5-NEXT: vspltish 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI30_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI30_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI30_1 at toc@l
+; PWR5-NEXT: vsrh 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 2
+; PWR5-NEXT: vsubuhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 4
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vmladduhm 2, 2, 4, 3
+; PWR5-NEXT: vspltish 3, 8
+; PWR5-NEXT: vsrh 2, 2, 3
+; PWR5-NEXT: vspltish 3, 10
+; PWR5-NEXT: vcmpgtuh 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_10_v8i16:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI30_0 at toc@ha
+; PWR6-NEXT: vspltish 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI30_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI30_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI30_1 at toc@l
+; PWR6-NEXT: vsrh 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 2
+; PWR6-NEXT: vsubuhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 4
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vmladduhm 2, 2, 4, 3
+; PWR6-NEXT: vspltish 3, 8
+; PWR6-NEXT: vsrh 2, 2, 3
+; PWR6-NEXT: vspltish 3, 10
+; PWR6-NEXT: vcmpgtuh 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_10_v8i16:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltish 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI30_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI30_0 at toc@l
+; PWR7-NEXT: vspltish 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI30_1 at toc@ha
+; PWR7-NEXT: vspltisb 5, 15
+; PWR7-NEXT: vsrh 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI30_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltish 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: vxor 4, 4, 4
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: xxland 34, 34, 37
+; PWR7-NEXT: vmladduhm 2, 2, 3, 4
+; PWR7-NEXT: vspltish 3, 8
+; PWR7-NEXT: vsrh 2, 2, 3
+; PWR7-NEXT: vspltish 3, 10
+; PWR7-NEXT: vcmpgtuh 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_10_v8i16:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltish 3, 10
+; PWR8-NEXT: vpopcnth 2, 2
+; PWR8-NEXT: vcmpgtuh 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_10_v8i16:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltish 3, 10
+; PWR9-NEXT: vpopcnth 2, 2
+; PWR9-NEXT: vcmpgtuh 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ugt <8 x i16> %2, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ult_11_v8i16(<8 x i16> %0) {
+; PWR5-LABEL: ult_11_v8i16:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI31_0 at toc@ha
+; PWR5-NEXT: vspltish 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI31_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI31_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI31_1 at toc@l
+; PWR5-NEXT: vsrh 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 2
+; PWR5-NEXT: vsubuhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 4
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vmladduhm 2, 2, 4, 3
+; PWR5-NEXT: vspltish 3, 8
+; PWR5-NEXT: vsrh 2, 2, 3
+; PWR5-NEXT: vspltish 3, 11
+; PWR5-NEXT: vcmpgtuh 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_11_v8i16:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI31_0 at toc@ha
+; PWR6-NEXT: vspltish 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI31_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI31_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI31_1 at toc@l
+; PWR6-NEXT: vsrh 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 2
+; PWR6-NEXT: vsubuhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 4
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vmladduhm 2, 2, 4, 3
+; PWR6-NEXT: vspltish 3, 8
+; PWR6-NEXT: vsrh 2, 2, 3
+; PWR6-NEXT: vspltish 3, 11
+; PWR6-NEXT: vcmpgtuh 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_11_v8i16:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltish 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI31_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI31_0 at toc@l
+; PWR7-NEXT: vspltish 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI31_1 at toc@ha
+; PWR7-NEXT: vspltisb 5, 15
+; PWR7-NEXT: vsrh 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI31_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltish 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: vxor 4, 4, 4
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: xxland 34, 34, 37
+; PWR7-NEXT: vmladduhm 2, 2, 3, 4
+; PWR7-NEXT: vspltish 3, 8
+; PWR7-NEXT: vsrh 2, 2, 3
+; PWR7-NEXT: vspltish 3, 11
+; PWR7-NEXT: vcmpgtuh 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_11_v8i16:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltish 3, 11
+; PWR8-NEXT: vpopcnth 2, 2
+; PWR8-NEXT: vcmpgtuh 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_11_v8i16:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltish 3, 11
+; PWR9-NEXT: vpopcnth 2, 2
+; PWR9-NEXT: vcmpgtuh 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ult <8 x i16> %2, <i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ugt_11_v8i16(<8 x i16> %0) {
+; PWR5-LABEL: ugt_11_v8i16:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI32_0 at toc@ha
+; PWR5-NEXT: vspltish 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI32_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI32_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI32_1 at toc@l
+; PWR5-NEXT: vsrh 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 2
+; PWR5-NEXT: vsubuhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 4
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vmladduhm 2, 2, 4, 3
+; PWR5-NEXT: vspltish 3, 8
+; PWR5-NEXT: vsrh 2, 2, 3
+; PWR5-NEXT: vspltish 3, 11
+; PWR5-NEXT: vcmpgtuh 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_11_v8i16:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI32_0 at toc@ha
+; PWR6-NEXT: vspltish 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI32_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI32_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI32_1 at toc@l
+; PWR6-NEXT: vsrh 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 2
+; PWR6-NEXT: vsubuhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 4
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vmladduhm 2, 2, 4, 3
+; PWR6-NEXT: vspltish 3, 8
+; PWR6-NEXT: vsrh 2, 2, 3
+; PWR6-NEXT: vspltish 3, 11
+; PWR6-NEXT: vcmpgtuh 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_11_v8i16:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltish 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI32_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI32_0 at toc@l
+; PWR7-NEXT: vspltish 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI32_1 at toc@ha
+; PWR7-NEXT: vspltisb 5, 15
+; PWR7-NEXT: vsrh 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI32_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltish 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: vxor 4, 4, 4
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: xxland 34, 34, 37
+; PWR7-NEXT: vmladduhm 2, 2, 3, 4
+; PWR7-NEXT: vspltish 3, 8
+; PWR7-NEXT: vsrh 2, 2, 3
+; PWR7-NEXT: vspltish 3, 11
+; PWR7-NEXT: vcmpgtuh 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_11_v8i16:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltish 3, 11
+; PWR8-NEXT: vpopcnth 2, 2
+; PWR8-NEXT: vcmpgtuh 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_11_v8i16:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltish 3, 11
+; PWR9-NEXT: vpopcnth 2, 2
+; PWR9-NEXT: vcmpgtuh 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ugt <8 x i16> %2, <i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ult_12_v8i16(<8 x i16> %0) {
+; PWR5-LABEL: ult_12_v8i16:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI33_0 at toc@ha
+; PWR5-NEXT: vspltish 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI33_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI33_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI33_1 at toc@l
+; PWR5-NEXT: vsrh 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 2
+; PWR5-NEXT: vsubuhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 4
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vmladduhm 2, 2, 4, 3
+; PWR5-NEXT: vspltish 3, 8
+; PWR5-NEXT: vsrh 2, 2, 3
+; PWR5-NEXT: vspltish 3, 12
+; PWR5-NEXT: vcmpgtuh 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_12_v8i16:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI33_0 at toc@ha
+; PWR6-NEXT: vspltish 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI33_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI33_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI33_1 at toc@l
+; PWR6-NEXT: vsrh 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 2
+; PWR6-NEXT: vsubuhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 4
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vmladduhm 2, 2, 4, 3
+; PWR6-NEXT: vspltish 3, 8
+; PWR6-NEXT: vsrh 2, 2, 3
+; PWR6-NEXT: vspltish 3, 12
+; PWR6-NEXT: vcmpgtuh 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_12_v8i16:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltish 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI33_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI33_0 at toc@l
+; PWR7-NEXT: vspltish 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI33_1 at toc@ha
+; PWR7-NEXT: vspltisb 5, 15
+; PWR7-NEXT: vsrh 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI33_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltish 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: vxor 4, 4, 4
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: xxland 34, 34, 37
+; PWR7-NEXT: vmladduhm 2, 2, 3, 4
+; PWR7-NEXT: vspltish 3, 8
+; PWR7-NEXT: vsrh 2, 2, 3
+; PWR7-NEXT: vspltish 3, 12
+; PWR7-NEXT: vcmpgtuh 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_12_v8i16:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltish 3, 12
+; PWR8-NEXT: vpopcnth 2, 2
+; PWR8-NEXT: vcmpgtuh 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_12_v8i16:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltish 3, 12
+; PWR9-NEXT: vpopcnth 2, 2
+; PWR9-NEXT: vcmpgtuh 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ult <8 x i16> %2, <i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ugt_12_v8i16(<8 x i16> %0) {
+; PWR5-LABEL: ugt_12_v8i16:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI34_0 at toc@ha
+; PWR5-NEXT: vspltish 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI34_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI34_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI34_1 at toc@l
+; PWR5-NEXT: vsrh 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 2
+; PWR5-NEXT: vsubuhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 4
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vmladduhm 2, 2, 4, 3
+; PWR5-NEXT: vspltish 3, 8
+; PWR5-NEXT: vsrh 2, 2, 3
+; PWR5-NEXT: vspltish 3, 12
+; PWR5-NEXT: vcmpgtuh 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_12_v8i16:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI34_0 at toc@ha
+; PWR6-NEXT: vspltish 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI34_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI34_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI34_1 at toc@l
+; PWR6-NEXT: vsrh 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 2
+; PWR6-NEXT: vsubuhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 4
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vmladduhm 2, 2, 4, 3
+; PWR6-NEXT: vspltish 3, 8
+; PWR6-NEXT: vsrh 2, 2, 3
+; PWR6-NEXT: vspltish 3, 12
+; PWR6-NEXT: vcmpgtuh 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_12_v8i16:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltish 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI34_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI34_0 at toc@l
+; PWR7-NEXT: vspltish 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI34_1 at toc@ha
+; PWR7-NEXT: vspltisb 5, 15
+; PWR7-NEXT: vsrh 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI34_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltish 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: vxor 4, 4, 4
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: xxland 34, 34, 37
+; PWR7-NEXT: vmladduhm 2, 2, 3, 4
+; PWR7-NEXT: vspltish 3, 8
+; PWR7-NEXT: vsrh 2, 2, 3
+; PWR7-NEXT: vspltish 3, 12
+; PWR7-NEXT: vcmpgtuh 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_12_v8i16:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltish 3, 12
+; PWR8-NEXT: vpopcnth 2, 2
+; PWR8-NEXT: vcmpgtuh 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_12_v8i16:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltish 3, 12
+; PWR9-NEXT: vpopcnth 2, 2
+; PWR9-NEXT: vcmpgtuh 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ugt <8 x i16> %2, <i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ult_13_v8i16(<8 x i16> %0) {
+; PWR5-LABEL: ult_13_v8i16:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI35_0 at toc@ha
+; PWR5-NEXT: vspltish 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI35_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI35_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI35_1 at toc@l
+; PWR5-NEXT: vsrh 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 2
+; PWR5-NEXT: vsubuhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 4
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vmladduhm 2, 2, 4, 3
+; PWR5-NEXT: vspltish 3, 8
+; PWR5-NEXT: vsrh 2, 2, 3
+; PWR5-NEXT: vspltish 3, 13
+; PWR5-NEXT: vcmpgtuh 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_13_v8i16:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI35_0 at toc@ha
+; PWR6-NEXT: vspltish 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI35_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI35_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI35_1 at toc@l
+; PWR6-NEXT: vsrh 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 2
+; PWR6-NEXT: vsubuhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 4
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vmladduhm 2, 2, 4, 3
+; PWR6-NEXT: vspltish 3, 8
+; PWR6-NEXT: vsrh 2, 2, 3
+; PWR6-NEXT: vspltish 3, 13
+; PWR6-NEXT: vcmpgtuh 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_13_v8i16:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltish 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI35_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI35_0 at toc@l
+; PWR7-NEXT: vspltish 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI35_1 at toc@ha
+; PWR7-NEXT: vspltisb 5, 15
+; PWR7-NEXT: vsrh 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI35_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltish 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: vxor 4, 4, 4
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: xxland 34, 34, 37
+; PWR7-NEXT: vmladduhm 2, 2, 3, 4
+; PWR7-NEXT: vspltish 3, 8
+; PWR7-NEXT: vsrh 2, 2, 3
+; PWR7-NEXT: vspltish 3, 13
+; PWR7-NEXT: vcmpgtuh 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_13_v8i16:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltish 3, 13
+; PWR8-NEXT: vpopcnth 2, 2
+; PWR8-NEXT: vcmpgtuh 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_13_v8i16:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltish 3, 13
+; PWR9-NEXT: vpopcnth 2, 2
+; PWR9-NEXT: vcmpgtuh 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ult <8 x i16> %2, <i16 13, i16 13, i16 13, i16 13, i16 13, i16 13, i16 13, i16 13>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ugt_13_v8i16(<8 x i16> %0) {
+; PWR5-LABEL: ugt_13_v8i16:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI36_0 at toc@ha
+; PWR5-NEXT: vspltish 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI36_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI36_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI36_1 at toc@l
+; PWR5-NEXT: vsrh 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 2
+; PWR5-NEXT: vsubuhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 4
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vmladduhm 2, 2, 4, 3
+; PWR5-NEXT: vspltish 3, 8
+; PWR5-NEXT: vsrh 2, 2, 3
+; PWR5-NEXT: vspltish 3, 13
+; PWR5-NEXT: vcmpgtuh 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_13_v8i16:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI36_0 at toc@ha
+; PWR6-NEXT: vspltish 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI36_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI36_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI36_1 at toc@l
+; PWR6-NEXT: vsrh 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 2
+; PWR6-NEXT: vsubuhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 4
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vmladduhm 2, 2, 4, 3
+; PWR6-NEXT: vspltish 3, 8
+; PWR6-NEXT: vsrh 2, 2, 3
+; PWR6-NEXT: vspltish 3, 13
+; PWR6-NEXT: vcmpgtuh 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_13_v8i16:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltish 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI36_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI36_0 at toc@l
+; PWR7-NEXT: vspltish 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI36_1 at toc@ha
+; PWR7-NEXT: vspltisb 5, 15
+; PWR7-NEXT: vsrh 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI36_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltish 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: vxor 4, 4, 4
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: xxland 34, 34, 37
+; PWR7-NEXT: vmladduhm 2, 2, 3, 4
+; PWR7-NEXT: vspltish 3, 8
+; PWR7-NEXT: vsrh 2, 2, 3
+; PWR7-NEXT: vspltish 3, 13
+; PWR7-NEXT: vcmpgtuh 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_13_v8i16:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltish 3, 13
+; PWR8-NEXT: vpopcnth 2, 2
+; PWR8-NEXT: vcmpgtuh 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_13_v8i16:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltish 3, 13
+; PWR9-NEXT: vpopcnth 2, 2
+; PWR9-NEXT: vcmpgtuh 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ugt <8 x i16> %2, <i16 13, i16 13, i16 13, i16 13, i16 13, i16 13, i16 13, i16 13>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ult_14_v8i16(<8 x i16> %0) {
+; PWR5-LABEL: ult_14_v8i16:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI37_0 at toc@ha
+; PWR5-NEXT: vspltish 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI37_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI37_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI37_1 at toc@l
+; PWR5-NEXT: vsrh 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 2
+; PWR5-NEXT: vsubuhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 4
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vmladduhm 2, 2, 4, 3
+; PWR5-NEXT: vspltish 3, 8
+; PWR5-NEXT: vsrh 2, 2, 3
+; PWR5-NEXT: vspltish 3, 14
+; PWR5-NEXT: vcmpgtuh 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_14_v8i16:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI37_0 at toc@ha
+; PWR6-NEXT: vspltish 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI37_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI37_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI37_1 at toc@l
+; PWR6-NEXT: vsrh 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 2
+; PWR6-NEXT: vsubuhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 4
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vmladduhm 2, 2, 4, 3
+; PWR6-NEXT: vspltish 3, 8
+; PWR6-NEXT: vsrh 2, 2, 3
+; PWR6-NEXT: vspltish 3, 14
+; PWR6-NEXT: vcmpgtuh 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_14_v8i16:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltish 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI37_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI37_0 at toc@l
+; PWR7-NEXT: vspltish 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI37_1 at toc@ha
+; PWR7-NEXT: vspltisb 5, 15
+; PWR7-NEXT: vsrh 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI37_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltish 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: vxor 4, 4, 4
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: xxland 34, 34, 37
+; PWR7-NEXT: vmladduhm 2, 2, 3, 4
+; PWR7-NEXT: vspltish 3, 8
+; PWR7-NEXT: vsrh 2, 2, 3
+; PWR7-NEXT: vspltish 3, 14
+; PWR7-NEXT: vcmpgtuh 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_14_v8i16:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltish 3, 14
+; PWR8-NEXT: vpopcnth 2, 2
+; PWR8-NEXT: vcmpgtuh 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_14_v8i16:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltish 3, 14
+; PWR9-NEXT: vpopcnth 2, 2
+; PWR9-NEXT: vcmpgtuh 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ult <8 x i16> %2, <i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ugt_14_v8i16(<8 x i16> %0) {
+; PWR5-LABEL: ugt_14_v8i16:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI38_0 at toc@ha
+; PWR5-NEXT: vspltish 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI38_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI38_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI38_1 at toc@l
+; PWR5-NEXT: vsrh 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 2
+; PWR5-NEXT: vsubuhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 4
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vmladduhm 2, 2, 4, 3
+; PWR5-NEXT: vspltish 3, 8
+; PWR5-NEXT: vsrh 2, 2, 3
+; PWR5-NEXT: vspltish 3, 14
+; PWR5-NEXT: vcmpgtuh 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_14_v8i16:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI38_0 at toc@ha
+; PWR6-NEXT: vspltish 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI38_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI38_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI38_1 at toc@l
+; PWR6-NEXT: vsrh 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 2
+; PWR6-NEXT: vsubuhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 4
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vmladduhm 2, 2, 4, 3
+; PWR6-NEXT: vspltish 3, 8
+; PWR6-NEXT: vsrh 2, 2, 3
+; PWR6-NEXT: vspltish 3, 14
+; PWR6-NEXT: vcmpgtuh 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_14_v8i16:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltish 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI38_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI38_0 at toc@l
+; PWR7-NEXT: vspltish 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI38_1 at toc@ha
+; PWR7-NEXT: vspltisb 5, 15
+; PWR7-NEXT: vsrh 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI38_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltish 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: vxor 4, 4, 4
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: xxland 34, 34, 37
+; PWR7-NEXT: vmladduhm 2, 2, 3, 4
+; PWR7-NEXT: vspltish 3, 8
+; PWR7-NEXT: vsrh 2, 2, 3
+; PWR7-NEXT: vspltish 3, 14
+; PWR7-NEXT: vcmpgtuh 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_14_v8i16:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltish 3, 14
+; PWR8-NEXT: vpopcnth 2, 2
+; PWR8-NEXT: vcmpgtuh 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_14_v8i16:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltish 3, 14
+; PWR9-NEXT: vpopcnth 2, 2
+; PWR9-NEXT: vcmpgtuh 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ugt <8 x i16> %2, <i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <8 x i16> @ult_15_v8i16(<8 x i16> %0) {
+; PWR5-LABEL: ult_15_v8i16:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI39_0 at toc@ha
+; PWR5-NEXT: vspltish 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI39_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI39_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI39_1 at toc@l
+; PWR5-NEXT: vsrh 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 2
+; PWR5-NEXT: vsubuhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: vspltish 5, 4
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vsrh 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduhm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vmladduhm 2, 2, 4, 3
+; PWR5-NEXT: vspltish 3, 8
+; PWR5-NEXT: vsrh 2, 2, 3
+; PWR5-NEXT: vspltish 3, 15
+; PWR5-NEXT: vcmpgtuh 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_15_v8i16:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI39_0 at toc@ha
+; PWR6-NEXT: vspltish 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI39_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI39_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI39_1 at toc@l
+; PWR6-NEXT: vsrh 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 2
+; PWR6-NEXT: vsubuhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: vspltish 5, 4
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vsrh 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduhm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vmladduhm 2, 2, 4, 3
+; PWR6-NEXT: vspltish 3, 8
+; PWR6-NEXT: vsrh 2, 2, 3
+; PWR6-NEXT: vspltish 3, 15
+; PWR6-NEXT: vcmpgtuh 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_15_v8i16:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltish 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI39_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI39_0 at toc@l
+; PWR7-NEXT: vspltish 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI39_1 at toc@ha
+; PWR7-NEXT: vspltisb 5, 15
+; PWR7-NEXT: vsrh 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI39_1 at toc@l
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltish 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vsrh 3, 2, 4
+; PWR7-NEXT: vxor 4, 4, 4
+; PWR7-NEXT: vadduhm 2, 2, 3
+; PWR7-NEXT: vspltisb 3, 1
+; PWR7-NEXT: xxland 34, 34, 37
+; PWR7-NEXT: vmladduhm 2, 2, 3, 4
+; PWR7-NEXT: vspltish 3, 8
+; PWR7-NEXT: vsrh 2, 2, 3
+; PWR7-NEXT: vspltish 3, 15
+; PWR7-NEXT: vcmpgtuh 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_15_v8i16:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltish 3, 15
+; PWR8-NEXT: vpopcnth 2, 2
+; PWR8-NEXT: vcmpgtuh 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_15_v8i16:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltish 3, 15
+; PWR9-NEXT: vpopcnth 2, 2
+; PWR9-NEXT: vcmpgtuh 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
+ %3 = icmp ult <8 x i16> %2, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+ %4 = sext <8 x i1> %3 to <8 x i16>
+ ret <8 x i16> %4
+}
+
+define <4 x i32> @ugt_1_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_1_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: vspltisb 3, -1
+; PWR5-NEXT: vadduwm 3, 2, 3
+; PWR5-NEXT: vand 2, 2, 3
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: vcmpequw 2, 2, 3
+; PWR5-NEXT: vnot 2, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_1_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: vspltisb 3, -1
+; PWR6-NEXT: vadduwm 3, 2, 3
+; PWR6-NEXT: vand 2, 2, 3
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: vcmpequw 2, 2, 3
+; PWR6-NEXT: vnot 2, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_1_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisb 3, -1
+; PWR7-NEXT: vadduwm 3, 2, 3
+; PWR7-NEXT: xxland 34, 34, 35
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: vcmpequw 2, 2, 3
+; PWR7-NEXT: xxlnor 34, 34, 34
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_1_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 1
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_1_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vspltisw 3, 1
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 1, i32 1, i32 1, i32 1>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_2_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_2_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: vspltisb 3, -1
+; PWR5-NEXT: vadduwm 3, 2, 3
+; PWR5-NEXT: vand 2, 2, 3
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: vcmpequw 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_2_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: vspltisb 3, -1
+; PWR6-NEXT: vadduwm 3, 2, 3
+; PWR6-NEXT: vand 2, 2, 3
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: vcmpequw 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_2_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisb 3, -1
+; PWR7-NEXT: vadduwm 3, 2, 3
+; PWR7-NEXT: xxland 34, 34, 35
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: vcmpequw 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_2_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 2
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_2_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vspltisw 3, 2
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 2, i32 2, i32 2, i32 2>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_2_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_2_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI42_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI42_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI42_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI42_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 1, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 1, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vcmpgtuw 2, 2, 0
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_2_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI42_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI42_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI42_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI42_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 1, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 1, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vcmpgtuw 2, 2, 0
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_2_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI42_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI42_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI42_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, 4
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI42_1 at toc@l
+; PWR7-NEXT: vspltisw 0, -16
+; PWR7-NEXT: vspltisb 1, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 5
+; PWR7-NEXT: vspltisb 5, 1
+; PWR7-NEXT: vrlw 6, 5, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 33
+; PWR7-NEXT: vmsumuhm 3, 2, 6, 3
+; PWR7-NEXT: vmulouh 2, 2, 5
+; PWR7-NEXT: vspltisw 5, 12
+; PWR7-NEXT: vslw 3, 3, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 5, 5
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vcmpgtuw 2, 2, 4
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_2_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 2
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_2_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vspltisw 3, 2
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 2, i32 2, i32 2, i32 2>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_3_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_3_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI43_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI43_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI43_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI43_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 3
+; PWR5-NEXT: vcmpgtuw 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_3_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI43_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI43_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI43_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI43_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 3
+; PWR6-NEXT: vcmpgtuw 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_3_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI43_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI43_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI43_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI43_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 3
+; PWR7-NEXT: vcmpgtuw 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_3_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 3
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_3_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vspltisw 3, 3
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 3, i32 3, i32 3, i32 3>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_3_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_3_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI44_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI44_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI44_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI44_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 3
+; PWR5-NEXT: vcmpgtuw 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_3_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI44_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI44_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI44_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI44_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 3
+; PWR6-NEXT: vcmpgtuw 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_3_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI44_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI44_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI44_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI44_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 3
+; PWR7-NEXT: vcmpgtuw 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_3_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 3
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_3_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vspltisw 3, 3
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 3, i32 3, i32 3, i32 3>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_4_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_4_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI45_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI45_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI45_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI45_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vspltisb 0, 15
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 0
+; PWR5-NEXT: vspltisw 0, -16
+; PWR5-NEXT: vrlw 1, 4, 0
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 1, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 0
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vcmpgtuw 2, 5, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_4_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI45_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI45_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI45_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI45_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vspltisb 0, 15
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 0
+; PWR6-NEXT: vspltisw 0, -16
+; PWR6-NEXT: vrlw 1, 4, 0
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 1, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 0
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vcmpgtuw 2, 5, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_4_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI45_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI45_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI45_1 at toc@ha
+; PWR7-NEXT: vspltisb 5, 1
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI45_1 at toc@l
+; PWR7-NEXT: vspltisw 0, -16
+; PWR7-NEXT: vspltisb 1, 15
+; PWR7-NEXT: vrlw 6, 5, 0
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 33
+; PWR7-NEXT: vmsumuhm 3, 2, 6, 3
+; PWR7-NEXT: vmulouh 2, 2, 5
+; PWR7-NEXT: vspltisw 5, 12
+; PWR7-NEXT: vslw 3, 3, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 5, 5
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vcmpgtuw 2, 4, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_4_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 4
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_4_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vspltisw 3, 4
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 4, i32 4, i32 4, i32 4>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_4_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_4_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI46_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI46_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI46_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI46_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vspltisb 0, 15
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 0
+; PWR5-NEXT: vspltisw 0, -16
+; PWR5-NEXT: vrlw 1, 4, 0
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 1, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 0
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vcmpgtuw 2, 2, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_4_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI46_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI46_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI46_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI46_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vspltisb 0, 15
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 0
+; PWR6-NEXT: vspltisw 0, -16
+; PWR6-NEXT: vrlw 1, 4, 0
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 1, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 0
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vcmpgtuw 2, 2, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_4_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI46_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI46_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI46_1 at toc@ha
+; PWR7-NEXT: vspltisb 5, 1
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI46_1 at toc@l
+; PWR7-NEXT: vspltisw 0, -16
+; PWR7-NEXT: vspltisb 1, 15
+; PWR7-NEXT: vrlw 6, 5, 0
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 33
+; PWR7-NEXT: vmsumuhm 3, 2, 6, 3
+; PWR7-NEXT: vmulouh 2, 2, 5
+; PWR7-NEXT: vspltisw 5, 12
+; PWR7-NEXT: vslw 3, 3, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 5, 5
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vcmpgtuw 2, 2, 4
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_4_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 4
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_4_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vspltisw 3, 4
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 4, i32 4, i32 4, i32 4>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_5_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_5_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI47_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI47_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI47_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI47_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 5
+; PWR5-NEXT: vcmpgtuw 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_5_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI47_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI47_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI47_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI47_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 5
+; PWR6-NEXT: vcmpgtuw 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_5_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI47_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI47_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI47_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI47_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 5
+; PWR7-NEXT: vcmpgtuw 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_5_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 5
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_5_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vspltisw 3, 5
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 5, i32 5, i32 5, i32 5>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_5_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_5_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI48_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI48_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI48_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI48_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 5
+; PWR5-NEXT: vcmpgtuw 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_5_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI48_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI48_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI48_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI48_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 5
+; PWR6-NEXT: vcmpgtuw 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_5_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI48_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI48_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI48_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI48_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 5
+; PWR7-NEXT: vcmpgtuw 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_5_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 5
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_5_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vspltisw 3, 5
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 5, i32 5, i32 5, i32 5>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_6_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_6_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI49_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI49_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI49_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI49_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 6
+; PWR5-NEXT: vcmpgtuw 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_6_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI49_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI49_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI49_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI49_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 6
+; PWR6-NEXT: vcmpgtuw 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_6_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI49_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI49_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI49_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI49_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 6
+; PWR7-NEXT: vcmpgtuw 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_6_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 6
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_6_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vspltisw 3, 6
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 6, i32 6, i32 6, i32 6>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_6_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_6_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI50_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI50_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI50_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI50_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 6
+; PWR5-NEXT: vcmpgtuw 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_6_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI50_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI50_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI50_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI50_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 6
+; PWR6-NEXT: vcmpgtuw 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_6_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI50_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI50_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI50_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI50_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 6
+; PWR7-NEXT: vcmpgtuw 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_6_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 6
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_6_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vspltisw 3, 6
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 6, i32 6, i32 6, i32 6>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_7_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_7_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI51_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI51_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI51_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI51_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 7
+; PWR5-NEXT: vcmpgtuw 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_7_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI51_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI51_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI51_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI51_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 7
+; PWR6-NEXT: vcmpgtuw 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_7_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI51_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI51_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI51_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI51_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 7
+; PWR7-NEXT: vcmpgtuw 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_7_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 7
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_7_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vspltisw 3, 7
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 7, i32 7, i32 7, i32 7>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_7_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_7_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI52_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI52_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI52_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI52_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 7
+; PWR5-NEXT: vcmpgtuw 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_7_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI52_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI52_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI52_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI52_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 7
+; PWR6-NEXT: vcmpgtuw 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_7_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI52_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI52_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI52_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI52_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 7
+; PWR7-NEXT: vcmpgtuw 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_7_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 7
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_7_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vspltisw 3, 7
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 7, i32 7, i32 7, i32 7>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_8_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_8_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI53_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI53_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI53_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI53_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 8
+; PWR5-NEXT: vcmpgtuw 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_8_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI53_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI53_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI53_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI53_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 8
+; PWR6-NEXT: vcmpgtuw 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_8_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI53_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI53_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI53_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI53_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 8
+; PWR7-NEXT: vcmpgtuw 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_8_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 8
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_8_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vspltisw 3, 8
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 8, i32 8, i32 8, i32 8>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_8_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_8_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI54_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI54_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI54_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI54_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 8
+; PWR5-NEXT: vcmpgtuw 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_8_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI54_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI54_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI54_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI54_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 8
+; PWR6-NEXT: vcmpgtuw 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_8_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI54_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI54_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI54_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI54_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 8
+; PWR7-NEXT: vcmpgtuw 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_8_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 8
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_8_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vspltisw 3, 8
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 8, i32 8, i32 8, i32 8>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_9_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_9_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI55_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI55_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI55_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI55_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 9
+; PWR5-NEXT: vcmpgtuw 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_9_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI55_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI55_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI55_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI55_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 9
+; PWR6-NEXT: vcmpgtuw 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_9_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI55_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI55_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI55_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI55_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 9
+; PWR7-NEXT: vcmpgtuw 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_9_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 9
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_9_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vspltisw 3, 9
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 9, i32 9, i32 9, i32 9>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_9_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_9_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI56_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI56_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI56_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI56_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 9
+; PWR5-NEXT: vcmpgtuw 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_9_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI56_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI56_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI56_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI56_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 9
+; PWR6-NEXT: vcmpgtuw 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_9_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI56_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI56_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI56_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI56_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 9
+; PWR7-NEXT: vcmpgtuw 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_9_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 9
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_9_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vspltisw 3, 9
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 9, i32 9, i32 9, i32 9>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_10_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_10_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI57_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI57_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI57_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI57_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 10
+; PWR5-NEXT: vcmpgtuw 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_10_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI57_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI57_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI57_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI57_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 10
+; PWR6-NEXT: vcmpgtuw 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_10_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI57_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI57_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI57_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI57_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 10
+; PWR7-NEXT: vcmpgtuw 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_10_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 10
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_10_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vspltisw 3, 10
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 10, i32 10, i32 10, i32 10>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_10_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_10_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI58_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI58_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI58_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI58_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 10
+; PWR5-NEXT: vcmpgtuw 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_10_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI58_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI58_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI58_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI58_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 10
+; PWR6-NEXT: vcmpgtuw 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_10_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI58_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI58_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI58_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI58_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 10
+; PWR7-NEXT: vcmpgtuw 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_10_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 10
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_10_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vspltisw 3, 10
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 10, i32 10, i32 10, i32 10>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_11_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_11_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI59_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI59_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI59_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI59_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 11
+; PWR5-NEXT: vcmpgtuw 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_11_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI59_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI59_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI59_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI59_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 11
+; PWR6-NEXT: vcmpgtuw 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_11_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI59_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI59_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI59_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI59_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 11
+; PWR7-NEXT: vcmpgtuw 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_11_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 11
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_11_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vspltisw 3, 11
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 11, i32 11, i32 11, i32 11>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_11_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_11_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI60_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI60_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI60_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI60_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 11
+; PWR5-NEXT: vcmpgtuw 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_11_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI60_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI60_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI60_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI60_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 11
+; PWR6-NEXT: vcmpgtuw 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_11_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI60_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI60_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI60_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI60_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 11
+; PWR7-NEXT: vcmpgtuw 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_11_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 11
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_11_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vspltisw 3, 11
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 11, i32 11, i32 11, i32 11>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_12_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_12_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI61_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI61_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI61_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI61_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 5, 3, 3
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 5
+; PWR5-NEXT: vcmpgtuw 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_12_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI61_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI61_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI61_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI61_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 5, 3, 3
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 5
+; PWR6-NEXT: vcmpgtuw 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_12_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI61_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI61_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI61_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI61_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vcmpgtuw 2, 4, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_12_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 12
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_12_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vspltisw 3, 12
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 12, i32 12, i32 12, i32 12>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_12_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_12_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI62_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI62_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI62_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI62_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 5, 3, 3
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 5
+; PWR5-NEXT: vcmpgtuw 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_12_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI62_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI62_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI62_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI62_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 5, 3, 3
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 5
+; PWR6-NEXT: vcmpgtuw 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_12_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI62_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI62_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI62_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI62_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vcmpgtuw 2, 2, 4
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_12_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 12
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_12_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vspltisw 3, 12
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 12, i32 12, i32 12, i32 12>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_13_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_13_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI63_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI63_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI63_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI63_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 13
+; PWR5-NEXT: vcmpgtuw 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_13_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI63_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI63_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI63_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI63_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 13
+; PWR6-NEXT: vcmpgtuw 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_13_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI63_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI63_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI63_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI63_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 13
+; PWR7-NEXT: vcmpgtuw 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_13_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 13
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_13_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vspltisw 3, 13
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 13, i32 13, i32 13, i32 13>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_13_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_13_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI64_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI64_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI64_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI64_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 13
+; PWR5-NEXT: vcmpgtuw 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_13_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI64_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI64_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI64_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI64_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 13
+; PWR6-NEXT: vcmpgtuw 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_13_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI64_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI64_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI64_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI64_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 13
+; PWR7-NEXT: vcmpgtuw 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_13_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 13
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_13_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vspltisw 3, 13
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 13, i32 13, i32 13, i32 13>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_14_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_14_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI65_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI65_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI65_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI65_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 14
+; PWR5-NEXT: vcmpgtuw 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_14_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI65_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI65_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI65_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI65_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 14
+; PWR6-NEXT: vcmpgtuw 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_14_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI65_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI65_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI65_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI65_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 14
+; PWR7-NEXT: vcmpgtuw 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_14_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 14
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_14_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vspltisw 3, 14
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 14, i32 14, i32 14, i32 14>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_14_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_14_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI66_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI66_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI66_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI66_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 14
+; PWR5-NEXT: vcmpgtuw 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_14_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI66_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI66_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI66_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI66_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 14
+; PWR6-NEXT: vcmpgtuw 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_14_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI66_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI66_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI66_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI66_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 14
+; PWR7-NEXT: vcmpgtuw 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_14_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 14
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_14_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vspltisw 3, 14
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 14, i32 14, i32 14, i32 14>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_15_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_15_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI67_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI67_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI67_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI67_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 15
+; PWR5-NEXT: vcmpgtuw 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_15_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI67_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI67_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI67_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI67_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 15
+; PWR6-NEXT: vcmpgtuw 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_15_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI67_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI67_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI67_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI67_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 15
+; PWR7-NEXT: vcmpgtuw 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_15_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 15
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_15_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vspltisw 3, 15
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 15, i32 15, i32 15, i32 15>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_15_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_15_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI68_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI68_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI68_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI68_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 15
+; PWR5-NEXT: vcmpgtuw 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_15_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI68_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI68_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI68_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI68_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 15
+; PWR6-NEXT: vcmpgtuw 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_15_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI68_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI68_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI68_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI68_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 15
+; PWR7-NEXT: vcmpgtuw 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_15_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 15
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_15_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vspltisw 3, 15
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 15, i32 15, i32 15, i32 15>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_16_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_16_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI69_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI69_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI69_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI69_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 8
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vcmpgtuw 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_16_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI69_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI69_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI69_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI69_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 8
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vcmpgtuw 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_16_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI69_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI69_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI69_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI69_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 8
+; PWR7-NEXT: vadduwm 3, 3, 3
+; PWR7-NEXT: vcmpgtuw 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_16_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 8
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vadduwm 3, 3, 3
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_16_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, 8
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vadduwm 3, 3, 3
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 16, i32 16, i32 16, i32 16>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_16_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_16_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI70_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI70_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI70_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI70_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 8
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vcmpgtuw 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_16_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI70_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI70_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI70_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI70_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 8
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vcmpgtuw 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_16_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI70_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI70_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI70_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI70_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 8
+; PWR7-NEXT: vadduwm 3, 3, 3
+; PWR7-NEXT: vcmpgtuw 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_16_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 8
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vadduwm 3, 3, 3
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_16_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, 8
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vadduwm 3, 3, 3
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 16, i32 16, i32 16, i32 16>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_17_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_17_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI71_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI71_0 at toc@l
+; PWR5-NEXT: lvx 0, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI71_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI71_1 at toc@l
+; PWR5-NEXT: vspltisw 1, 2
+; PWR5-NEXT: vsrw 5, 2, 4
+; PWR5-NEXT: vand 5, 5, 0
+; PWR5-NEXT: lvx 0, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 5
+; PWR5-NEXT: vand 5, 2, 0
+; PWR5-NEXT: vsrw 2, 2, 1
+; PWR5-NEXT: vand 2, 2, 0
+; PWR5-NEXT: vspltisw 0, 4
+; PWR5-NEXT: vadduwm 2, 5, 2
+; PWR5-NEXT: vsrw 5, 2, 0
+; PWR5-NEXT: vspltisb 0, 15
+; PWR5-NEXT: vadduwm 2, 2, 5
+; PWR5-NEXT: vspltisb 5, 1
+; PWR5-NEXT: vand 2, 2, 0
+; PWR5-NEXT: vspltisw 0, -16
+; PWR5-NEXT: vrlw 1, 5, 0
+; PWR5-NEXT: vmulouh 5, 2, 5
+; PWR5-NEXT: vmsumuhm 2, 2, 1, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 0
+; PWR5-NEXT: vadduwm 2, 5, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vsubuwm 3, 4, 0
+; PWR5-NEXT: vcmpgtuw 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_17_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI71_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI71_0 at toc@l
+; PWR6-NEXT: lvx 0, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI71_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI71_1 at toc@l
+; PWR6-NEXT: vspltisw 1, 2
+; PWR6-NEXT: vsrw 5, 2, 4
+; PWR6-NEXT: vand 5, 5, 0
+; PWR6-NEXT: lvx 0, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 5
+; PWR6-NEXT: vand 5, 2, 0
+; PWR6-NEXT: vsrw 2, 2, 1
+; PWR6-NEXT: vand 2, 2, 0
+; PWR6-NEXT: vspltisw 0, 4
+; PWR6-NEXT: vadduwm 2, 5, 2
+; PWR6-NEXT: vsrw 5, 2, 0
+; PWR6-NEXT: vspltisb 0, 15
+; PWR6-NEXT: vadduwm 2, 2, 5
+; PWR6-NEXT: vspltisb 5, 1
+; PWR6-NEXT: vand 2, 2, 0
+; PWR6-NEXT: vspltisw 0, -16
+; PWR6-NEXT: vrlw 1, 5, 0
+; PWR6-NEXT: vmulouh 5, 2, 5
+; PWR6-NEXT: vmsumuhm 2, 2, 1, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 0
+; PWR6-NEXT: vadduwm 2, 5, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vsubuwm 3, 4, 0
+; PWR6-NEXT: vcmpgtuw 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_17_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI71_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI71_0 at toc@l
+; PWR7-NEXT: vspltisw 5, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI71_1 at toc@ha
+; PWR7-NEXT: vspltisw 0, -16
+; PWR7-NEXT: vsrw 4, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI71_1 at toc@l
+; PWR7-NEXT: vspltisb 1, 15
+; PWR7-NEXT: vsubuwm 3, 3, 0
+; PWR7-NEXT: xxland 36, 36, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 4
+; PWR7-NEXT: vsrw 4, 2, 5
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 5, 4
+; PWR7-NEXT: xxland 36, 36, 0
+; PWR7-NEXT: vadduwm 2, 2, 4
+; PWR7-NEXT: vsrw 4, 2, 5
+; PWR7-NEXT: vspltisb 5, 1
+; PWR7-NEXT: vrlw 6, 5, 0
+; PWR7-NEXT: vadduwm 2, 2, 4
+; PWR7-NEXT: xxlxor 36, 36, 36
+; PWR7-NEXT: xxland 34, 34, 33
+; PWR7-NEXT: vmsumuhm 4, 2, 6, 4
+; PWR7-NEXT: vmulouh 2, 2, 5
+; PWR7-NEXT: vspltisw 5, 12
+; PWR7-NEXT: vslw 4, 4, 0
+; PWR7-NEXT: vadduwm 2, 2, 4
+; PWR7-NEXT: vadduwm 4, 5, 5
+; PWR7-NEXT: vsrw 2, 2, 4
+; PWR7-NEXT: vcmpgtuw 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_17_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, -16
+; PWR8-NEXT: vspltisw 4, 1
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vsubuwm 3, 4, 3
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_17_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, -16
+; PWR9-NEXT: vspltisw 4, 1
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vsubuwm 3, 4, 3
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 17, i32 17, i32 17, i32 17>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_17_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_17_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI72_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI72_0 at toc@l
+; PWR5-NEXT: lvx 0, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI72_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI72_1 at toc@l
+; PWR5-NEXT: vspltisw 1, 2
+; PWR5-NEXT: vsrw 5, 2, 4
+; PWR5-NEXT: vand 5, 5, 0
+; PWR5-NEXT: lvx 0, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 5
+; PWR5-NEXT: vand 5, 2, 0
+; PWR5-NEXT: vsrw 2, 2, 1
+; PWR5-NEXT: vand 2, 2, 0
+; PWR5-NEXT: vspltisw 0, 4
+; PWR5-NEXT: vadduwm 2, 5, 2
+; PWR5-NEXT: vsrw 5, 2, 0
+; PWR5-NEXT: vspltisb 0, 15
+; PWR5-NEXT: vadduwm 2, 2, 5
+; PWR5-NEXT: vspltisb 5, 1
+; PWR5-NEXT: vand 2, 2, 0
+; PWR5-NEXT: vspltisw 0, -16
+; PWR5-NEXT: vrlw 1, 5, 0
+; PWR5-NEXT: vmulouh 5, 2, 5
+; PWR5-NEXT: vmsumuhm 2, 2, 1, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 0
+; PWR5-NEXT: vadduwm 2, 5, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vsubuwm 3, 4, 0
+; PWR5-NEXT: vcmpgtuw 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_17_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI72_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI72_0 at toc@l
+; PWR6-NEXT: lvx 0, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI72_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI72_1 at toc@l
+; PWR6-NEXT: vspltisw 1, 2
+; PWR6-NEXT: vsrw 5, 2, 4
+; PWR6-NEXT: vand 5, 5, 0
+; PWR6-NEXT: lvx 0, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 5
+; PWR6-NEXT: vand 5, 2, 0
+; PWR6-NEXT: vsrw 2, 2, 1
+; PWR6-NEXT: vand 2, 2, 0
+; PWR6-NEXT: vspltisw 0, 4
+; PWR6-NEXT: vadduwm 2, 5, 2
+; PWR6-NEXT: vsrw 5, 2, 0
+; PWR6-NEXT: vspltisb 0, 15
+; PWR6-NEXT: vadduwm 2, 2, 5
+; PWR6-NEXT: vspltisb 5, 1
+; PWR6-NEXT: vand 2, 2, 0
+; PWR6-NEXT: vspltisw 0, -16
+; PWR6-NEXT: vrlw 1, 5, 0
+; PWR6-NEXT: vmulouh 5, 2, 5
+; PWR6-NEXT: vmsumuhm 2, 2, 1, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 0
+; PWR6-NEXT: vadduwm 2, 5, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vsubuwm 3, 4, 0
+; PWR6-NEXT: vcmpgtuw 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_17_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI72_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI72_0 at toc@l
+; PWR7-NEXT: vspltisw 5, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI72_1 at toc@ha
+; PWR7-NEXT: vspltisw 0, -16
+; PWR7-NEXT: vsrw 4, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI72_1 at toc@l
+; PWR7-NEXT: vspltisb 1, 15
+; PWR7-NEXT: vsubuwm 3, 3, 0
+; PWR7-NEXT: xxland 36, 36, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 4
+; PWR7-NEXT: vsrw 4, 2, 5
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 5, 4
+; PWR7-NEXT: xxland 36, 36, 0
+; PWR7-NEXT: vadduwm 2, 2, 4
+; PWR7-NEXT: vsrw 4, 2, 5
+; PWR7-NEXT: vspltisb 5, 1
+; PWR7-NEXT: vrlw 6, 5, 0
+; PWR7-NEXT: vadduwm 2, 2, 4
+; PWR7-NEXT: xxlxor 36, 36, 36
+; PWR7-NEXT: xxland 34, 34, 33
+; PWR7-NEXT: vmsumuhm 4, 2, 6, 4
+; PWR7-NEXT: vmulouh 2, 2, 5
+; PWR7-NEXT: vspltisw 5, 12
+; PWR7-NEXT: vslw 4, 4, 0
+; PWR7-NEXT: vadduwm 2, 2, 4
+; PWR7-NEXT: vadduwm 4, 5, 5
+; PWR7-NEXT: vsrw 2, 2, 4
+; PWR7-NEXT: vcmpgtuw 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_17_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, -16
+; PWR8-NEXT: vspltisw 4, 1
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vsubuwm 3, 4, 3
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_17_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, -16
+; PWR9-NEXT: vspltisw 4, 1
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vsubuwm 3, 4, 3
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 17, i32 17, i32 17, i32 17>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_18_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_18_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI73_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI73_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI73_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI73_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 9
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vcmpgtuw 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_18_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI73_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI73_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI73_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI73_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 9
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vcmpgtuw 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_18_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI73_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI73_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI73_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI73_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 9
+; PWR7-NEXT: vadduwm 3, 3, 3
+; PWR7-NEXT: vcmpgtuw 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_18_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 9
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vadduwm 3, 3, 3
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_18_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, 9
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vadduwm 3, 3, 3
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 18, i32 18, i32 18, i32 18>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_18_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_18_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI74_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI74_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI74_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI74_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 9
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vcmpgtuw 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_18_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI74_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI74_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI74_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI74_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 9
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vcmpgtuw 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_18_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI74_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI74_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI74_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI74_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 9
+; PWR7-NEXT: vadduwm 3, 3, 3
+; PWR7-NEXT: vcmpgtuw 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_18_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 9
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vadduwm 3, 3, 3
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_18_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, 9
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vadduwm 3, 3, 3
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 18, i32 18, i32 18, i32 18>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_19_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_19_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI75_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI75_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI75_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI75_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 3
+; PWR5-NEXT: vsubuwm 3, 3, 5
+; PWR5-NEXT: vcmpgtuw 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_19_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI75_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI75_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI75_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI75_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 3
+; PWR6-NEXT: vsubuwm 3, 3, 5
+; PWR6-NEXT: vcmpgtuw 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_19_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI75_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI75_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI75_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI75_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 3
+; PWR7-NEXT: vsubuwm 3, 3, 5
+; PWR7-NEXT: vcmpgtuw 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_19_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, -16
+; PWR8-NEXT: vspltisw 4, 3
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vsubuwm 3, 4, 3
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_19_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, -16
+; PWR9-NEXT: vspltisw 4, 3
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vsubuwm 3, 4, 3
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 19, i32 19, i32 19, i32 19>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_19_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_19_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI76_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI76_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI76_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI76_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 3
+; PWR5-NEXT: vsubuwm 3, 3, 5
+; PWR5-NEXT: vcmpgtuw 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_19_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI76_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI76_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI76_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI76_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 3
+; PWR6-NEXT: vsubuwm 3, 3, 5
+; PWR6-NEXT: vcmpgtuw 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_19_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI76_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI76_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI76_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI76_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 3
+; PWR7-NEXT: vsubuwm 3, 3, 5
+; PWR7-NEXT: vcmpgtuw 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_19_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, -16
+; PWR8-NEXT: vspltisw 4, 3
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vsubuwm 3, 4, 3
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_19_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, -16
+; PWR9-NEXT: vspltisw 4, 3
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vsubuwm 3, 4, 3
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 19, i32 19, i32 19, i32 19>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_20_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_20_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI77_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI77_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI77_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI77_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 10
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vcmpgtuw 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_20_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI77_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI77_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI77_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI77_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 10
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vcmpgtuw 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_20_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI77_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI77_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI77_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI77_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 10
+; PWR7-NEXT: vadduwm 3, 3, 3
+; PWR7-NEXT: vcmpgtuw 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_20_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 10
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vadduwm 3, 3, 3
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_20_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, 10
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vadduwm 3, 3, 3
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 20, i32 20, i32 20, i32 20>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_20_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_20_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI78_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI78_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI78_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI78_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 10
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vcmpgtuw 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_20_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI78_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI78_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI78_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI78_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 10
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vcmpgtuw 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_20_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI78_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI78_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI78_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI78_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 10
+; PWR7-NEXT: vadduwm 3, 3, 3
+; PWR7-NEXT: vcmpgtuw 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_20_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 10
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vadduwm 3, 3, 3
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_20_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, 10
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vadduwm 3, 3, 3
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 20, i32 20, i32 20, i32 20>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_21_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_21_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI79_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI79_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI79_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI79_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 5
+; PWR5-NEXT: vsubuwm 3, 3, 5
+; PWR5-NEXT: vcmpgtuw 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_21_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI79_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI79_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI79_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI79_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 5
+; PWR6-NEXT: vsubuwm 3, 3, 5
+; PWR6-NEXT: vcmpgtuw 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_21_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI79_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI79_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI79_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI79_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 5
+; PWR7-NEXT: vsubuwm 3, 3, 5
+; PWR7-NEXT: vcmpgtuw 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_21_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, -16
+; PWR8-NEXT: vspltisw 4, 5
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vsubuwm 3, 4, 3
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_21_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, -16
+; PWR9-NEXT: vspltisw 4, 5
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vsubuwm 3, 4, 3
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 21, i32 21, i32 21, i32 21>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_21_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_21_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI80_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI80_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI80_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI80_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 5
+; PWR5-NEXT: vsubuwm 3, 3, 5
+; PWR5-NEXT: vcmpgtuw 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_21_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI80_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI80_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI80_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI80_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 5
+; PWR6-NEXT: vsubuwm 3, 3, 5
+; PWR6-NEXT: vcmpgtuw 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_21_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI80_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI80_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI80_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI80_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 5
+; PWR7-NEXT: vsubuwm 3, 3, 5
+; PWR7-NEXT: vcmpgtuw 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_21_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, -16
+; PWR8-NEXT: vspltisw 4, 5
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vsubuwm 3, 4, 3
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_21_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, -16
+; PWR9-NEXT: vspltisw 4, 5
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vsubuwm 3, 4, 3
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 21, i32 21, i32 21, i32 21>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_22_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_22_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI81_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI81_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI81_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI81_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 11
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vcmpgtuw 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_22_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI81_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI81_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI81_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI81_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 11
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vcmpgtuw 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_22_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI81_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI81_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI81_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI81_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 11
+; PWR7-NEXT: vadduwm 3, 3, 3
+; PWR7-NEXT: vcmpgtuw 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_22_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 11
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vadduwm 3, 3, 3
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_22_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, 11
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vadduwm 3, 3, 3
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 22, i32 22, i32 22, i32 22>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_22_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_22_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI82_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI82_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI82_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI82_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 11
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vcmpgtuw 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_22_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI82_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI82_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI82_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI82_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 11
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vcmpgtuw 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_22_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI82_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI82_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI82_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI82_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 11
+; PWR7-NEXT: vadduwm 3, 3, 3
+; PWR7-NEXT: vcmpgtuw 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_22_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 11
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vadduwm 3, 3, 3
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_22_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, 11
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vadduwm 3, 3, 3
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 22, i32 22, i32 22, i32 22>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_23_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_23_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI83_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI83_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI83_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI83_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 7
+; PWR5-NEXT: vsubuwm 3, 3, 5
+; PWR5-NEXT: vcmpgtuw 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_23_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI83_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI83_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI83_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI83_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 7
+; PWR6-NEXT: vsubuwm 3, 3, 5
+; PWR6-NEXT: vcmpgtuw 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_23_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI83_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI83_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI83_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI83_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 7
+; PWR7-NEXT: vsubuwm 3, 3, 5
+; PWR7-NEXT: vcmpgtuw 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_23_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, -16
+; PWR8-NEXT: vspltisw 4, 7
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vsubuwm 3, 4, 3
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_23_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, -16
+; PWR9-NEXT: vspltisw 4, 7
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vsubuwm 3, 4, 3
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 23, i32 23, i32 23, i32 23>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_23_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_23_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI84_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI84_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI84_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI84_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 7
+; PWR5-NEXT: vsubuwm 3, 3, 5
+; PWR5-NEXT: vcmpgtuw 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_23_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI84_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI84_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI84_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI84_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 7
+; PWR6-NEXT: vsubuwm 3, 3, 5
+; PWR6-NEXT: vcmpgtuw 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_23_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI84_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI84_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI84_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI84_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 7
+; PWR7-NEXT: vsubuwm 3, 3, 5
+; PWR7-NEXT: vcmpgtuw 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_23_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, -16
+; PWR8-NEXT: vspltisw 4, 7
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vsubuwm 3, 4, 3
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_23_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, -16
+; PWR9-NEXT: vspltisw 4, 7
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vsubuwm 3, 4, 3
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 23, i32 23, i32 23, i32 23>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_24_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_24_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI85_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI85_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI85_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI85_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vcmpgtuw 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_24_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI85_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI85_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI85_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI85_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vcmpgtuw 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_24_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI85_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI85_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI85_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI85_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vcmpgtuw 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_24_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 12
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vadduwm 3, 3, 3
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_24_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, 12
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vadduwm 3, 3, 3
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 24, i32 24, i32 24, i32 24>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_24_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_24_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI86_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI86_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI86_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI86_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vcmpgtuw 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_24_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI86_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI86_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI86_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI86_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vcmpgtuw 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_24_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI86_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI86_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI86_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI86_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vcmpgtuw 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_24_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 12
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vadduwm 3, 3, 3
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_24_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, 12
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vadduwm 3, 3, 3
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 24, i32 24, i32 24, i32 24>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_25_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_25_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI87_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI87_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI87_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI87_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 9
+; PWR5-NEXT: vsubuwm 3, 3, 5
+; PWR5-NEXT: vcmpgtuw 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_25_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI87_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI87_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI87_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI87_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 9
+; PWR6-NEXT: vsubuwm 3, 3, 5
+; PWR6-NEXT: vcmpgtuw 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_25_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI87_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI87_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI87_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI87_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 9
+; PWR7-NEXT: vsubuwm 3, 3, 5
+; PWR7-NEXT: vcmpgtuw 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_25_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, -16
+; PWR8-NEXT: vspltisw 4, 9
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vsubuwm 3, 4, 3
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_25_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, -16
+; PWR9-NEXT: vspltisw 4, 9
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vsubuwm 3, 4, 3
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 25, i32 25, i32 25, i32 25>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_25_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_25_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI88_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI88_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI88_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI88_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 9
+; PWR5-NEXT: vsubuwm 3, 3, 5
+; PWR5-NEXT: vcmpgtuw 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_25_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI88_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI88_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI88_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI88_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 9
+; PWR6-NEXT: vsubuwm 3, 3, 5
+; PWR6-NEXT: vcmpgtuw 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_25_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI88_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI88_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI88_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI88_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 9
+; PWR7-NEXT: vsubuwm 3, 3, 5
+; PWR7-NEXT: vcmpgtuw 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_25_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, -16
+; PWR8-NEXT: vspltisw 4, 9
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vsubuwm 3, 4, 3
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_25_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, -16
+; PWR9-NEXT: vspltisw 4, 9
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vsubuwm 3, 4, 3
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 25, i32 25, i32 25, i32 25>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_26_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_26_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI89_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI89_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI89_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI89_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 13
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vcmpgtuw 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_26_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI89_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI89_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI89_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI89_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 13
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vcmpgtuw 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_26_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI89_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI89_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI89_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI89_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 13
+; PWR7-NEXT: vadduwm 3, 3, 3
+; PWR7-NEXT: vcmpgtuw 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_26_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 13
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vadduwm 3, 3, 3
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_26_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, 13
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vadduwm 3, 3, 3
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 26, i32 26, i32 26, i32 26>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_26_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_26_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI90_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI90_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI90_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI90_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 13
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vcmpgtuw 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_26_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI90_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI90_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI90_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI90_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 13
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vcmpgtuw 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_26_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI90_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI90_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI90_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI90_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 13
+; PWR7-NEXT: vadduwm 3, 3, 3
+; PWR7-NEXT: vcmpgtuw 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_26_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 13
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vadduwm 3, 3, 3
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_26_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, 13
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vadduwm 3, 3, 3
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 26, i32 26, i32 26, i32 26>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_27_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_27_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI91_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI91_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI91_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI91_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 11
+; PWR5-NEXT: vsubuwm 3, 3, 5
+; PWR5-NEXT: vcmpgtuw 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_27_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI91_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI91_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI91_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI91_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 11
+; PWR6-NEXT: vsubuwm 3, 3, 5
+; PWR6-NEXT: vcmpgtuw 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_27_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI91_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI91_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI91_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI91_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 11
+; PWR7-NEXT: vsubuwm 3, 3, 5
+; PWR7-NEXT: vcmpgtuw 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_27_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, -16
+; PWR8-NEXT: vspltisw 4, 11
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vsubuwm 3, 4, 3
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_27_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, -16
+; PWR9-NEXT: vspltisw 4, 11
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vsubuwm 3, 4, 3
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 27, i32 27, i32 27, i32 27>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_27_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_27_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI92_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI92_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI92_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI92_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 11
+; PWR5-NEXT: vsubuwm 3, 3, 5
+; PWR5-NEXT: vcmpgtuw 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_27_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI92_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI92_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI92_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI92_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 11
+; PWR6-NEXT: vsubuwm 3, 3, 5
+; PWR6-NEXT: vcmpgtuw 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_27_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI92_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI92_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI92_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI92_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 11
+; PWR7-NEXT: vsubuwm 3, 3, 5
+; PWR7-NEXT: vcmpgtuw 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_27_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, -16
+; PWR8-NEXT: vspltisw 4, 11
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vsubuwm 3, 4, 3
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_27_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, -16
+; PWR9-NEXT: vspltisw 4, 11
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vsubuwm 3, 4, 3
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 27, i32 27, i32 27, i32 27>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_28_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_28_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI93_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI93_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI93_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI93_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 14
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vcmpgtuw 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_28_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI93_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI93_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI93_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI93_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 14
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vcmpgtuw 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_28_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI93_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI93_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI93_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI93_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 14
+; PWR7-NEXT: vadduwm 3, 3, 3
+; PWR7-NEXT: vcmpgtuw 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_28_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 14
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vadduwm 3, 3, 3
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_28_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, 14
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vadduwm 3, 3, 3
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 28, i32 28, i32 28, i32 28>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_28_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_28_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI94_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI94_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI94_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI94_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 14
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vcmpgtuw 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_28_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI94_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI94_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI94_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI94_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 14
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vcmpgtuw 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_28_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI94_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI94_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI94_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI94_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 14
+; PWR7-NEXT: vadduwm 3, 3, 3
+; PWR7-NEXT: vcmpgtuw 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_28_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 14
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vadduwm 3, 3, 3
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_28_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, 14
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vadduwm 3, 3, 3
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 28, i32 28, i32 28, i32 28>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_29_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_29_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI95_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI95_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI95_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI95_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 13
+; PWR5-NEXT: vsubuwm 3, 3, 5
+; PWR5-NEXT: vcmpgtuw 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_29_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI95_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI95_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI95_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI95_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 13
+; PWR6-NEXT: vsubuwm 3, 3, 5
+; PWR6-NEXT: vcmpgtuw 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_29_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI95_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI95_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI95_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI95_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 13
+; PWR7-NEXT: vsubuwm 3, 3, 5
+; PWR7-NEXT: vcmpgtuw 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_29_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, -16
+; PWR8-NEXT: vspltisw 4, 13
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vsubuwm 3, 4, 3
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_29_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, -16
+; PWR9-NEXT: vspltisw 4, 13
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vsubuwm 3, 4, 3
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 29, i32 29, i32 29, i32 29>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_29_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_29_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI96_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI96_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI96_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI96_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 13
+; PWR5-NEXT: vsubuwm 3, 3, 5
+; PWR5-NEXT: vcmpgtuw 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_29_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI96_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI96_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI96_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI96_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 13
+; PWR6-NEXT: vsubuwm 3, 3, 5
+; PWR6-NEXT: vcmpgtuw 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_29_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI96_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI96_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI96_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI96_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 13
+; PWR7-NEXT: vsubuwm 3, 3, 5
+; PWR7-NEXT: vcmpgtuw 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_29_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, -16
+; PWR8-NEXT: vspltisw 4, 13
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vsubuwm 3, 4, 3
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_29_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, -16
+; PWR9-NEXT: vspltisw 4, 13
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vsubuwm 3, 4, 3
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 29, i32 29, i32 29, i32 29>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_30_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_30_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI97_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI97_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI97_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI97_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 15
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vcmpgtuw 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_30_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI97_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI97_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI97_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI97_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 15
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vcmpgtuw 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_30_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI97_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI97_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI97_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI97_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 15
+; PWR7-NEXT: vadduwm 3, 3, 3
+; PWR7-NEXT: vcmpgtuw 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_30_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 15
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vadduwm 3, 3, 3
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_30_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, 15
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vadduwm 3, 3, 3
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 30, i32 30, i32 30, i32 30>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ugt_30_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ugt_30_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI98_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI98_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI98_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI98_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 15
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vcmpgtuw 2, 2, 3
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_30_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI98_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI98_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI98_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI98_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 15
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vcmpgtuw 2, 2, 3
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_30_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI98_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI98_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI98_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI98_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 15
+; PWR7-NEXT: vadduwm 3, 3, 3
+; PWR7-NEXT: vcmpgtuw 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_30_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, 15
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vadduwm 3, 3, 3
+; PWR8-NEXT: vcmpgtuw 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_30_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, 15
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vadduwm 3, 3, 3
+; PWR9-NEXT: vcmpgtuw 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ugt <4 x i32> %2, <i32 30, i32 30, i32 30, i32 30>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @ult_31_v4i32(<4 x i32> %0) {
+; PWR5-LABEL: ult_31_v4i32:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addis 3, 2, .LCPI99_0 at toc@ha
+; PWR5-NEXT: vspltisw 4, 1
+; PWR5-NEXT: vxor 3, 3, 3
+; PWR5-NEXT: addi 3, 3, .LCPI99_0 at toc@l
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: addis 3, 2, .LCPI99_1 at toc@ha
+; PWR5-NEXT: addi 3, 3, .LCPI99_1 at toc@l
+; PWR5-NEXT: vspltisw 0, 2
+; PWR5-NEXT: vsrw 4, 2, 4
+; PWR5-NEXT: vand 4, 4, 5
+; PWR5-NEXT: lvx 5, 0, 3
+; PWR5-NEXT: vsubuwm 2, 2, 4
+; PWR5-NEXT: vand 4, 2, 5
+; PWR5-NEXT: vsrw 2, 2, 0
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, 4
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 4, 2, 5
+; PWR5-NEXT: vspltisb 5, 15
+; PWR5-NEXT: vadduwm 2, 2, 4
+; PWR5-NEXT: vspltisb 4, 1
+; PWR5-NEXT: vand 2, 2, 5
+; PWR5-NEXT: vspltisw 5, -16
+; PWR5-NEXT: vrlw 0, 4, 5
+; PWR5-NEXT: vmulouh 4, 2, 4
+; PWR5-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR5-NEXT: vspltisw 3, 12
+; PWR5-NEXT: vadduwm 3, 3, 3
+; PWR5-NEXT: vslw 2, 2, 5
+; PWR5-NEXT: vadduwm 2, 4, 2
+; PWR5-NEXT: vsrw 2, 2, 3
+; PWR5-NEXT: vspltisw 3, 15
+; PWR5-NEXT: vsubuwm 3, 3, 5
+; PWR5-NEXT: vcmpgtuw 2, 3, 2
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_31_v4i32:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addis 3, 2, .LCPI99_0 at toc@ha
+; PWR6-NEXT: vspltisw 4, 1
+; PWR6-NEXT: vxor 3, 3, 3
+; PWR6-NEXT: addi 3, 3, .LCPI99_0 at toc@l
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: addis 3, 2, .LCPI99_1 at toc@ha
+; PWR6-NEXT: addi 3, 3, .LCPI99_1 at toc@l
+; PWR6-NEXT: vspltisw 0, 2
+; PWR6-NEXT: vsrw 4, 2, 4
+; PWR6-NEXT: vand 4, 4, 5
+; PWR6-NEXT: lvx 5, 0, 3
+; PWR6-NEXT: vsubuwm 2, 2, 4
+; PWR6-NEXT: vand 4, 2, 5
+; PWR6-NEXT: vsrw 2, 2, 0
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, 4
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 4, 2, 5
+; PWR6-NEXT: vspltisb 5, 15
+; PWR6-NEXT: vadduwm 2, 2, 4
+; PWR6-NEXT: vspltisb 4, 1
+; PWR6-NEXT: vand 2, 2, 5
+; PWR6-NEXT: vspltisw 5, -16
+; PWR6-NEXT: vrlw 0, 4, 5
+; PWR6-NEXT: vmulouh 4, 2, 4
+; PWR6-NEXT: vmsumuhm 2, 2, 0, 3
+; PWR6-NEXT: vspltisw 3, 12
+; PWR6-NEXT: vadduwm 3, 3, 3
+; PWR6-NEXT: vslw 2, 2, 5
+; PWR6-NEXT: vadduwm 2, 4, 2
+; PWR6-NEXT: vsrw 2, 2, 3
+; PWR6-NEXT: vspltisw 3, 15
+; PWR6-NEXT: vsubuwm 3, 3, 5
+; PWR6-NEXT: vcmpgtuw 2, 3, 2
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_31_v4i32:
+; PWR7: # %bb.0:
+; PWR7-NEXT: vspltisw 3, 1
+; PWR7-NEXT: addis 3, 2, .LCPI99_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI99_0 at toc@l
+; PWR7-NEXT: vspltisw 4, 2
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI99_1 at toc@ha
+; PWR7-NEXT: vspltisw 5, -16
+; PWR7-NEXT: vsrw 3, 2, 3
+; PWR7-NEXT: addi 3, 3, .LCPI99_1 at toc@l
+; PWR7-NEXT: vspltisb 0, 15
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: vsubuwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vspltisw 4, 4
+; PWR7-NEXT: xxland 35, 35, 0
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vsrw 3, 2, 4
+; PWR7-NEXT: vspltisb 4, 1
+; PWR7-NEXT: vrlw 1, 4, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: xxlxor 35, 35, 35
+; PWR7-NEXT: xxland 34, 34, 32
+; PWR7-NEXT: vmsumuhm 3, 2, 1, 3
+; PWR7-NEXT: vmulouh 2, 2, 4
+; PWR7-NEXT: vspltisw 4, 12
+; PWR7-NEXT: vslw 3, 3, 5
+; PWR7-NEXT: vadduwm 2, 2, 3
+; PWR7-NEXT: vadduwm 3, 4, 4
+; PWR7-NEXT: vsrw 2, 2, 3
+; PWR7-NEXT: vspltisw 3, 15
+; PWR7-NEXT: vsubuwm 3, 3, 5
+; PWR7-NEXT: vcmpgtuw 2, 3, 2
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_31_v4i32:
+; PWR8: # %bb.0:
+; PWR8-NEXT: vspltisw 3, -16
+; PWR8-NEXT: vspltisw 4, 15
+; PWR8-NEXT: vpopcntw 2, 2
+; PWR8-NEXT: vsubuwm 3, 4, 3
+; PWR8-NEXT: vcmpgtuw 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_31_v4i32:
+; PWR9: # %bb.0:
+; PWR9-NEXT: vspltisw 3, -16
+; PWR9-NEXT: vspltisw 4, 15
+; PWR9-NEXT: vpopcntw 2, 2
+; PWR9-NEXT: vsubuwm 3, 4, 3
+; PWR9-NEXT: vcmpgtuw 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
+ %3 = icmp ult <4 x i32> %2, <i32 31, i32 31, i32 31, i32 31>
+ %4 = sext <4 x i1> %3 to <4 x i32>
+ ret <4 x i32> %4
+}
+
+define <2 x i64> @ugt_1_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_1_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addi 5, 3, -1
+; PWR5-NEXT: and 3, 3, 5
+; PWR5-NEXT: addi 5, 4, -1
+; PWR5-NEXT: subfic 3, 3, 0
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: and 4, 4, 5
+; PWR5-NEXT: subfic 4, 4, 0
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_1_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addi 5, 3, -1
+; PWR6-NEXT: and 3, 3, 5
+; PWR6-NEXT: addi 5, 4, -1
+; PWR6-NEXT: subfic 3, 3, 0
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: and 4, 4, 5
+; PWR6-NEXT: subfic 4, 4, 0
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_1_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: addi 3, 3, -1
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: ld 3, -32(1)
+; PWR7-NEXT: addi 3, 3, -1
+; PWR7-NEXT: std 3, -16(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI100_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI100_0 at toc@l
+; PWR7-NEXT: lxvw4x 35, 0, 3
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vcmpequw 2, 2, 3
+; PWR7-NEXT: xxlnor 34, 34, 34
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_1_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI100_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI100_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_1_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI100_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI100_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 1, i64 1>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_2_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_2_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: addi 5, 3, -1
+; PWR5-NEXT: and 3, 3, 5
+; PWR5-NEXT: addi 5, 4, -1
+; PWR5-NEXT: addic 3, 3, -1
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: and 4, 4, 5
+; PWR5-NEXT: addic 4, 4, -1
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_2_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: addi 5, 3, -1
+; PWR6-NEXT: and 3, 3, 5
+; PWR6-NEXT: addi 5, 4, -1
+; PWR6-NEXT: addic 3, 3, -1
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: and 4, 4, 5
+; PWR6-NEXT: addic 4, 4, -1
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_2_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: addi 3, 3, -1
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: ld 3, -32(1)
+; PWR7-NEXT: addi 3, 3, -1
+; PWR7-NEXT: std 3, -16(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI101_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI101_0 at toc@l
+; PWR7-NEXT: lxvw4x 35, 0, 3
+; PWR7-NEXT: xxland 34, 34, 0
+; PWR7-NEXT: vcmpequw 2, 2, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_2_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI101_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI101_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_2_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI101_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI101_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 2, i64 2>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_2_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_2_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 2
+; PWR5-NEXT: subfic 3, 3, 2
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 2
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_2_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 2
+; PWR6-NEXT: subfic 3, 3, 2
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 2
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_2_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 2
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 2
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_2_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI102_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI102_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_2_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI102_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI102_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 2, i64 2>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_3_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_3_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 3
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_3_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 3
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_3_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 3
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 3
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_3_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI103_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI103_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_3_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI103_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI103_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 3, i64 3>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_3_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_3_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 3
+; PWR5-NEXT: subfic 3, 3, 3
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 3
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_3_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 3
+; PWR6-NEXT: subfic 3, 3, 3
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 3
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_3_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 3
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 3
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_3_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI104_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI104_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_3_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI104_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI104_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 3, i64 3>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_4_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_4_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 4
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_4_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 4
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_4_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 4
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 4
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_4_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI105_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI105_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_4_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI105_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI105_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 4, i64 4>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_4_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_4_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 4
+; PWR5-NEXT: subfic 3, 3, 4
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 4
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_4_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 4
+; PWR6-NEXT: subfic 3, 3, 4
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 4
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_4_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 4
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 4
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_4_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI106_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI106_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_4_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI106_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI106_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 4, i64 4>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_5_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_5_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 5
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_5_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 5
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_5_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 5
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 5
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_5_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI107_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI107_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_5_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI107_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI107_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 5, i64 5>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_5_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_5_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 5
+; PWR5-NEXT: subfic 3, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 5
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_5_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 5
+; PWR6-NEXT: subfic 3, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 5
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_5_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 5
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 5
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_5_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI108_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI108_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_5_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI108_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI108_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 5, i64 5>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_6_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_6_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 6
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_6_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 6
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_6_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 6
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 6
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_6_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI109_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI109_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_6_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI109_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI109_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 6, i64 6>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_6_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_6_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 6
+; PWR5-NEXT: subfic 3, 3, 6
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 6
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_6_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 6
+; PWR6-NEXT: subfic 3, 3, 6
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 6
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_6_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 6
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 6
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_6_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI110_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI110_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_6_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI110_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI110_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 6, i64 6>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_7_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_7_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 7
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_7_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 7
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_7_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 7
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 7
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_7_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI111_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI111_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_7_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI111_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI111_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 7, i64 7>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_7_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_7_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 7
+; PWR5-NEXT: subfic 3, 3, 7
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 7
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_7_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 7
+; PWR6-NEXT: subfic 3, 3, 7
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 7
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_7_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 7
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 7
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_7_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI112_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI112_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_7_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI112_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI112_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 7, i64 7>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_8_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_8_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 8
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_8_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 8
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_8_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 8
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 8
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_8_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI113_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI113_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_8_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI113_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI113_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 8, i64 8>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_8_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_8_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 8
+; PWR5-NEXT: subfic 3, 3, 8
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 8
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_8_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 8
+; PWR6-NEXT: subfic 3, 3, 8
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 8
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_8_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 8
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 8
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_8_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI114_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI114_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_8_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI114_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI114_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 8, i64 8>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_9_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_9_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 9
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_9_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 9
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_9_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 9
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 9
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_9_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI115_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI115_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_9_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI115_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI115_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 9, i64 9>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_9_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_9_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 9
+; PWR5-NEXT: subfic 3, 3, 9
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 9
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_9_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 9
+; PWR6-NEXT: subfic 3, 3, 9
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 9
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_9_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 9
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 9
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_9_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI116_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI116_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_9_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI116_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI116_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 9, i64 9>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_10_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_10_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 10
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_10_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 10
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_10_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 10
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 10
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_10_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI117_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI117_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_10_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI117_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI117_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 10, i64 10>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_10_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_10_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 10
+; PWR5-NEXT: subfic 3, 3, 10
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 10
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_10_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 10
+; PWR6-NEXT: subfic 3, 3, 10
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 10
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_10_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 10
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 10
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_10_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI118_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI118_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_10_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI118_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI118_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 10, i64 10>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_11_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_11_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 11
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_11_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 11
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_11_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 11
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 11
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_11_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI119_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI119_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_11_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI119_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI119_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 11, i64 11>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_11_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_11_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 11
+; PWR5-NEXT: subfic 3, 3, 11
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 11
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_11_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 11
+; PWR6-NEXT: subfic 3, 3, 11
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 11
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_11_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 11
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 11
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_11_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI120_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI120_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_11_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI120_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI120_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 11, i64 11>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_12_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_12_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 12
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_12_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 12
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_12_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 12
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 12
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_12_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI121_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI121_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_12_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI121_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI121_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 12, i64 12>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_12_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_12_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 12
+; PWR5-NEXT: subfic 3, 3, 12
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 12
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_12_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 12
+; PWR6-NEXT: subfic 3, 3, 12
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 12
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_12_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 12
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 12
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_12_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI122_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI122_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_12_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI122_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI122_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 12, i64 12>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_13_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_13_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 13
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_13_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 13
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_13_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 13
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 13
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_13_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI123_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI123_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_13_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI123_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI123_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 13, i64 13>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_13_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_13_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 13
+; PWR5-NEXT: subfic 3, 3, 13
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 13
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_13_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 13
+; PWR6-NEXT: subfic 3, 3, 13
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 13
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_13_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 13
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 13
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_13_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI124_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI124_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_13_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI124_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI124_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 13, i64 13>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_14_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_14_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 14
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_14_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 14
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_14_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 14
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 14
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_14_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI125_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI125_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_14_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI125_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI125_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 14, i64 14>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_14_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_14_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 14
+; PWR5-NEXT: subfic 3, 3, 14
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 14
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_14_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 14
+; PWR6-NEXT: subfic 3, 3, 14
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 14
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_14_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 14
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 14
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_14_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI126_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI126_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_14_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI126_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI126_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 14, i64 14>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_15_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_15_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 15
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_15_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 15
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_15_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 15
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 15
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_15_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI127_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI127_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_15_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI127_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI127_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 15, i64 15>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_15_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_15_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 15
+; PWR5-NEXT: subfic 3, 3, 15
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 15
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_15_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 15
+; PWR6-NEXT: subfic 3, 3, 15
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 15
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_15_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 15
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 15
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_15_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI128_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI128_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_15_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI128_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI128_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 15, i64 15>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_16_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_16_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 16
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_16_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 16
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_16_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 16
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 16
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_16_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI129_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI129_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_16_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI129_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI129_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 16, i64 16>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_16_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_16_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 16
+; PWR5-NEXT: subfic 3, 3, 16
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 16
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_16_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 16
+; PWR6-NEXT: subfic 3, 3, 16
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 16
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_16_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 16
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 16
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_16_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI130_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI130_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_16_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI130_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI130_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 16, i64 16>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_17_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_17_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 17
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_17_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 17
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_17_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 17
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 17
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_17_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI131_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI131_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_17_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI131_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI131_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 17, i64 17>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_17_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_17_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 17
+; PWR5-NEXT: subfic 3, 3, 17
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 17
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_17_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 17
+; PWR6-NEXT: subfic 3, 3, 17
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 17
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_17_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 17
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 17
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_17_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI132_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI132_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_17_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI132_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI132_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 17, i64 17>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_18_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_18_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 18
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_18_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 18
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_18_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 18
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 18
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_18_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI133_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI133_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_18_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI133_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI133_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 18, i64 18>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_18_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_18_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 18
+; PWR5-NEXT: subfic 3, 3, 18
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 18
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_18_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 18
+; PWR6-NEXT: subfic 3, 3, 18
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 18
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_18_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 18
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 18
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_18_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI134_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI134_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_18_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI134_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI134_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 18, i64 18>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_19_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_19_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 19
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_19_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 19
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_19_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 19
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 19
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_19_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI135_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI135_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_19_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI135_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI135_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 19, i64 19>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_19_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_19_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 19
+; PWR5-NEXT: subfic 3, 3, 19
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 19
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_19_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 19
+; PWR6-NEXT: subfic 3, 3, 19
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 19
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_19_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 19
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 19
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_19_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI136_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI136_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_19_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI136_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI136_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 19, i64 19>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_20_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_20_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 20
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_20_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 20
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_20_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 20
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 20
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_20_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI137_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI137_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_20_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI137_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI137_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 20, i64 20>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_20_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_20_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 20
+; PWR5-NEXT: subfic 3, 3, 20
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 20
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_20_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 20
+; PWR6-NEXT: subfic 3, 3, 20
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 20
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_20_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 20
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 20
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_20_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI138_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI138_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_20_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI138_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI138_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 20, i64 20>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_21_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_21_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 21
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_21_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 21
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_21_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 21
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 21
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_21_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI139_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI139_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_21_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI139_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI139_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 21, i64 21>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_21_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_21_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 21
+; PWR5-NEXT: subfic 3, 3, 21
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 21
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_21_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 21
+; PWR6-NEXT: subfic 3, 3, 21
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 21
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_21_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 21
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 21
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_21_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI140_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI140_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_21_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI140_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI140_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 21, i64 21>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_22_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_22_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 22
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_22_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 22
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_22_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 22
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 22
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_22_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI141_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI141_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_22_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI141_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI141_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 22, i64 22>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_22_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_22_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 22
+; PWR5-NEXT: subfic 3, 3, 22
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 22
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_22_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 22
+; PWR6-NEXT: subfic 3, 3, 22
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 22
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_22_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 22
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 22
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_22_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI142_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI142_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_22_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI142_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI142_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 22, i64 22>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_23_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_23_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 23
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_23_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 23
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_23_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 23
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 23
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_23_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI143_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI143_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_23_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI143_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI143_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 23, i64 23>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_23_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_23_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 23
+; PWR5-NEXT: subfic 3, 3, 23
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 23
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_23_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 23
+; PWR6-NEXT: subfic 3, 3, 23
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 23
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_23_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 23
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 23
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_23_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI144_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI144_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_23_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI144_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI144_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 23, i64 23>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_24_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_24_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 24
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_24_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 24
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_24_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 24
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 24
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_24_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI145_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI145_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_24_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI145_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI145_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 24, i64 24>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_24_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_24_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 24
+; PWR5-NEXT: subfic 3, 3, 24
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 24
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_24_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 24
+; PWR6-NEXT: subfic 3, 3, 24
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 24
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_24_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 24
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 24
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_24_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI146_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI146_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_24_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI146_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI146_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 24, i64 24>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_25_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_25_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 25
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_25_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 25
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_25_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 25
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 25
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_25_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI147_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI147_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_25_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI147_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI147_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 25, i64 25>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_25_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_25_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 25
+; PWR5-NEXT: subfic 3, 3, 25
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 25
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_25_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 25
+; PWR6-NEXT: subfic 3, 3, 25
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 25
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_25_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 25
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 25
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_25_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI148_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI148_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_25_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI148_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI148_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 25, i64 25>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_26_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_26_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 26
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_26_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 26
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_26_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 26
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 26
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_26_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI149_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI149_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_26_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI149_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI149_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 26, i64 26>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_26_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_26_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 26
+; PWR5-NEXT: subfic 3, 3, 26
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 26
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_26_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 26
+; PWR6-NEXT: subfic 3, 3, 26
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 26
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_26_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 26
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 26
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_26_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI150_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI150_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_26_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI150_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI150_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 26, i64 26>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_27_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_27_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 27
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_27_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 27
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_27_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 27
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 27
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_27_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI151_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI151_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_27_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI151_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI151_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 27, i64 27>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_27_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_27_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 27
+; PWR5-NEXT: subfic 3, 3, 27
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 27
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_27_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 27
+; PWR6-NEXT: subfic 3, 3, 27
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 27
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_27_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 27
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 27
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_27_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI152_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI152_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_27_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI152_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI152_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 27, i64 27>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_28_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_28_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 28
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_28_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 28
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_28_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 28
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 28
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_28_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI153_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI153_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_28_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI153_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI153_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 28, i64 28>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_28_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_28_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 28
+; PWR5-NEXT: subfic 3, 3, 28
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 28
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_28_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 28
+; PWR6-NEXT: subfic 3, 3, 28
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 28
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_28_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 28
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 28
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_28_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI154_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI154_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_28_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI154_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI154_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 28, i64 28>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_29_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_29_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 29
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_29_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 29
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_29_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 29
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 29
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_29_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI155_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI155_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_29_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI155_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI155_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 29, i64 29>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_29_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_29_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 29
+; PWR5-NEXT: subfic 3, 3, 29
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 29
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_29_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 29
+; PWR6-NEXT: subfic 3, 3, 29
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 29
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_29_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 29
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 29
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_29_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI156_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI156_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_29_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI156_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI156_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 29, i64 29>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_30_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_30_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 30
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_30_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 30
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_30_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 30
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 30
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_30_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI157_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI157_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_30_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI157_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI157_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 30, i64 30>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_30_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_30_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 30
+; PWR5-NEXT: subfic 3, 3, 30
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 30
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_30_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 30
+; PWR6-NEXT: subfic 3, 3, 30
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 30
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_30_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 30
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 30
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_30_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI158_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI158_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_30_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI158_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI158_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 30, i64 30>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_31_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_31_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 31
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_31_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 31
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_31_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 31
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 31
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_31_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI159_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI159_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_31_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI159_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI159_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 31, i64 31>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_31_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_31_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 31
+; PWR5-NEXT: subfic 3, 3, 31
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 31
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_31_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 31
+; PWR6-NEXT: subfic 3, 3, 31
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 31
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_31_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 31
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 31
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_31_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI160_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI160_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_31_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI160_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI160_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 31, i64 31>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_32_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_32_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 32
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_32_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 32
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_32_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 32
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 32
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_32_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI161_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI161_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_32_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI161_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI161_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 32, i64 32>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_32_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_32_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 32
+; PWR5-NEXT: subfic 3, 3, 32
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 32
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_32_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 32
+; PWR6-NEXT: subfic 3, 3, 32
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 32
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_32_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 32
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 32
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_32_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI162_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI162_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_32_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI162_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI162_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 32, i64 32>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_33_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_33_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 33
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_33_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 33
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_33_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 33
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 33
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_33_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI163_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI163_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_33_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI163_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI163_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 33, i64 33>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_33_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_33_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 33
+; PWR5-NEXT: subfic 3, 3, 33
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 33
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_33_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 33
+; PWR6-NEXT: subfic 3, 3, 33
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 33
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_33_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 33
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 33
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_33_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI164_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI164_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_33_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI164_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI164_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 33, i64 33>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_34_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_34_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 34
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_34_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 34
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_34_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 34
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 34
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_34_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI165_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI165_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_34_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI165_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI165_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 34, i64 34>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_34_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_34_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 34
+; PWR5-NEXT: subfic 3, 3, 34
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 34
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_34_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 34
+; PWR6-NEXT: subfic 3, 3, 34
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 34
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_34_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 34
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 34
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_34_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI166_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI166_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_34_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI166_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI166_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 34, i64 34>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_35_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_35_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 35
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_35_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 35
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_35_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 35
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 35
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_35_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI167_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI167_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_35_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI167_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI167_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 35, i64 35>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_35_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_35_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 35
+; PWR5-NEXT: subfic 3, 3, 35
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 35
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_35_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 35
+; PWR6-NEXT: subfic 3, 3, 35
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 35
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_35_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 35
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 35
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_35_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI168_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI168_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_35_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI168_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI168_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 35, i64 35>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_36_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_36_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 36
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_36_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 36
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_36_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 36
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 36
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_36_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI169_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI169_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_36_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI169_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI169_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 36, i64 36>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_36_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_36_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 36
+; PWR5-NEXT: subfic 3, 3, 36
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 36
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_36_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 36
+; PWR6-NEXT: subfic 3, 3, 36
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 36
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_36_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 36
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 36
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_36_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI170_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI170_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_36_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI170_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI170_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 36, i64 36>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_37_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_37_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 37
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_37_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 37
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_37_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 37
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 37
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_37_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI171_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI171_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_37_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI171_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI171_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 37, i64 37>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_37_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_37_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 37
+; PWR5-NEXT: subfic 3, 3, 37
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 37
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_37_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 37
+; PWR6-NEXT: subfic 3, 3, 37
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 37
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_37_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 37
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 37
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_37_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI172_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI172_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_37_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI172_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI172_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 37, i64 37>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_38_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_38_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 38
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_38_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 38
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_38_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 38
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 38
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_38_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI173_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI173_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_38_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI173_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI173_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 38, i64 38>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_38_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_38_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 38
+; PWR5-NEXT: subfic 3, 3, 38
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 38
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_38_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 38
+; PWR6-NEXT: subfic 3, 3, 38
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 38
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_38_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 38
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 38
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_38_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI174_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI174_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_38_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI174_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI174_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 38, i64 38>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_39_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_39_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 39
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_39_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 39
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_39_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 39
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 39
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_39_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI175_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI175_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_39_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI175_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI175_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 39, i64 39>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_39_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_39_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 39
+; PWR5-NEXT: subfic 3, 3, 39
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 39
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_39_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 39
+; PWR6-NEXT: subfic 3, 3, 39
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 39
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_39_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 39
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 39
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_39_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI176_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI176_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_39_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI176_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI176_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 39, i64 39>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_40_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_40_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 40
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_40_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 40
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_40_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 40
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 40
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_40_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI177_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI177_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_40_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI177_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI177_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 40, i64 40>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_40_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_40_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 40
+; PWR5-NEXT: subfic 3, 3, 40
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 40
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_40_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 40
+; PWR6-NEXT: subfic 3, 3, 40
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 40
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_40_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 40
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 40
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_40_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI178_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI178_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_40_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI178_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI178_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 40, i64 40>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_41_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_41_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 41
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_41_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 41
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_41_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 41
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 41
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_41_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI179_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI179_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_41_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI179_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI179_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 41, i64 41>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_41_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_41_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 41
+; PWR5-NEXT: subfic 3, 3, 41
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 41
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_41_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 41
+; PWR6-NEXT: subfic 3, 3, 41
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 41
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_41_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 41
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 41
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_41_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI180_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI180_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_41_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI180_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI180_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 41, i64 41>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_42_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_42_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 42
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_42_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 42
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_42_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 42
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 42
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_42_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI181_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI181_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_42_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI181_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI181_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 42, i64 42>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_42_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_42_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 42
+; PWR5-NEXT: subfic 3, 3, 42
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 42
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_42_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 42
+; PWR6-NEXT: subfic 3, 3, 42
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 42
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_42_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 42
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 42
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_42_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI182_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI182_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_42_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI182_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI182_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 42, i64 42>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_43_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_43_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 43
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_43_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 43
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_43_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 43
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 43
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_43_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI183_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI183_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_43_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI183_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI183_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 43, i64 43>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_43_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_43_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 43
+; PWR5-NEXT: subfic 3, 3, 43
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 43
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_43_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 43
+; PWR6-NEXT: subfic 3, 3, 43
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 43
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_43_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 43
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 43
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_43_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI184_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI184_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_43_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI184_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI184_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 43, i64 43>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_44_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_44_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 44
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_44_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 44
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_44_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 44
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 44
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_44_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI185_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI185_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_44_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI185_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI185_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 44, i64 44>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_44_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_44_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 44
+; PWR5-NEXT: subfic 3, 3, 44
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 44
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_44_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 44
+; PWR6-NEXT: subfic 3, 3, 44
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 44
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_44_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 44
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 44
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_44_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI186_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI186_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_44_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI186_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI186_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 44, i64 44>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_45_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_45_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 45
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_45_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 45
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_45_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 45
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 45
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_45_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI187_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI187_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_45_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI187_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI187_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 45, i64 45>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_45_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_45_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 45
+; PWR5-NEXT: subfic 3, 3, 45
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 45
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_45_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 45
+; PWR6-NEXT: subfic 3, 3, 45
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 45
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_45_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 45
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 45
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_45_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI188_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI188_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_45_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI188_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI188_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 45, i64 45>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_46_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_46_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 46
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_46_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 46
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_46_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 46
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 46
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_46_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI189_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI189_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_46_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI189_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI189_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 46, i64 46>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_46_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_46_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 46
+; PWR5-NEXT: subfic 3, 3, 46
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 46
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_46_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 46
+; PWR6-NEXT: subfic 3, 3, 46
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 46
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_46_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 46
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 46
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_46_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI190_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI190_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_46_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI190_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI190_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 46, i64 46>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_47_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_47_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 47
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_47_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 47
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_47_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 47
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 47
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_47_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI191_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI191_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_47_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI191_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI191_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 47, i64 47>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_47_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_47_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 47
+; PWR5-NEXT: subfic 3, 3, 47
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 47
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_47_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 47
+; PWR6-NEXT: subfic 3, 3, 47
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 47
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_47_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 47
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 47
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_47_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI192_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI192_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_47_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI192_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI192_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 47, i64 47>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_48_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_48_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 48
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_48_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 48
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_48_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 48
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 48
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_48_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI193_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI193_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_48_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI193_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI193_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 48, i64 48>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_48_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_48_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 48
+; PWR5-NEXT: subfic 3, 3, 48
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 48
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_48_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 48
+; PWR6-NEXT: subfic 3, 3, 48
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 48
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_48_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 48
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 48
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_48_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI194_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI194_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_48_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI194_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI194_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 48, i64 48>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_49_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_49_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 49
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_49_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 49
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_49_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 49
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 49
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_49_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI195_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI195_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_49_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI195_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI195_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 49, i64 49>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_49_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_49_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 49
+; PWR5-NEXT: subfic 3, 3, 49
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 49
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_49_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 49
+; PWR6-NEXT: subfic 3, 3, 49
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 49
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_49_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 49
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 49
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_49_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI196_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI196_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_49_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI196_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI196_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 49, i64 49>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_50_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_50_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 50
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_50_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 50
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_50_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 50
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 50
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_50_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI197_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI197_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_50_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI197_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI197_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 50, i64 50>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_50_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_50_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 50
+; PWR5-NEXT: subfic 3, 3, 50
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 50
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_50_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 50
+; PWR6-NEXT: subfic 3, 3, 50
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 50
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_50_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 50
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 50
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_50_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI198_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI198_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_50_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI198_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI198_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 50, i64 50>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_51_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_51_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 51
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_51_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 51
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_51_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 51
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 51
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_51_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI199_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI199_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_51_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI199_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI199_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 51, i64 51>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_51_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_51_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 51
+; PWR5-NEXT: subfic 3, 3, 51
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 51
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_51_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 51
+; PWR6-NEXT: subfic 3, 3, 51
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 51
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_51_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 51
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 51
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_51_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI200_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI200_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_51_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI200_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI200_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 51, i64 51>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_52_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_52_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 52
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_52_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 52
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_52_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 52
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 52
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_52_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI201_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI201_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_52_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI201_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI201_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 52, i64 52>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_52_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_52_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 52
+; PWR5-NEXT: subfic 3, 3, 52
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 52
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_52_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 52
+; PWR6-NEXT: subfic 3, 3, 52
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 52
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_52_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 52
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 52
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_52_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI202_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI202_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_52_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI202_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI202_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 52, i64 52>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_53_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_53_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 53
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_53_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 53
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_53_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 53
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 53
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_53_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI203_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI203_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_53_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI203_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI203_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 53, i64 53>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_53_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_53_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 53
+; PWR5-NEXT: subfic 3, 3, 53
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 53
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_53_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 53
+; PWR6-NEXT: subfic 3, 3, 53
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 53
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_53_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 53
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 53
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_53_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI204_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI204_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_53_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI204_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI204_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 53, i64 53>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_54_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_54_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 54
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_54_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 54
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_54_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 54
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 54
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_54_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI205_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI205_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_54_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI205_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI205_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 54, i64 54>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_54_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_54_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 54
+; PWR5-NEXT: subfic 3, 3, 54
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 54
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_54_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 54
+; PWR6-NEXT: subfic 3, 3, 54
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 54
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_54_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 54
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 54
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_54_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI206_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI206_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_54_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI206_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI206_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 54, i64 54>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_55_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_55_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 55
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_55_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 55
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_55_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 55
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 55
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_55_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI207_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI207_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_55_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI207_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI207_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 55, i64 55>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_55_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_55_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 55
+; PWR5-NEXT: subfic 3, 3, 55
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 55
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_55_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 55
+; PWR6-NEXT: subfic 3, 3, 55
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 55
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_55_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 55
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 55
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_55_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI208_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI208_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_55_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI208_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI208_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 55, i64 55>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_56_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_56_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_56_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_56_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 56
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 56
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_56_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI209_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI209_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_56_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI209_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI209_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 56, i64 56>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_56_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_56_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 56
+; PWR5-NEXT: subfic 3, 3, 56
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 56
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_56_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 56
+; PWR6-NEXT: subfic 3, 3, 56
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 56
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_56_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 56
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 56
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_56_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI210_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI210_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_56_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI210_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI210_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 56, i64 56>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_57_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_57_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 57
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_57_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 57
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_57_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 57
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 57
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_57_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI211_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI211_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_57_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI211_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI211_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 57, i64 57>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_57_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_57_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 57
+; PWR5-NEXT: subfic 3, 3, 57
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 57
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_57_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 57
+; PWR6-NEXT: subfic 3, 3, 57
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 57
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_57_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 57
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 57
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_57_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI212_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI212_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_57_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI212_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI212_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 57, i64 57>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_58_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_58_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 58
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_58_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 58
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_58_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 58
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 58
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_58_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI213_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI213_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_58_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI213_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI213_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 58, i64 58>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_58_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_58_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 58
+; PWR5-NEXT: subfic 3, 3, 58
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 58
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_58_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 58
+; PWR6-NEXT: subfic 3, 3, 58
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 58
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_58_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 58
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 58
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_58_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI214_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI214_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_58_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI214_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI214_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 58, i64 58>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_59_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_59_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 59
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_59_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 59
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_59_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 59
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 59
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_59_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI215_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI215_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_59_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI215_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI215_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 59, i64 59>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_59_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_59_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 59
+; PWR5-NEXT: subfic 3, 3, 59
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 59
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_59_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 59
+; PWR6-NEXT: subfic 3, 3, 59
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 59
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_59_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 59
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 59
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_59_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI216_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI216_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_59_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI216_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI216_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 59, i64 59>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_60_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_60_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 60
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_60_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 60
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_60_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 60
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 60
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_60_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI217_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI217_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_60_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI217_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI217_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 60, i64 60>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_60_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_60_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 60
+; PWR5-NEXT: subfic 3, 3, 60
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 60
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_60_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 60
+; PWR6-NEXT: subfic 3, 3, 60
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 60
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_60_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 60
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 60
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_60_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI218_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI218_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_60_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI218_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI218_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 60, i64 60>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_61_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_61_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 61
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_61_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 61
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_61_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 61
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 61
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_61_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI219_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI219_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_61_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI219_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI219_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 61, i64 61>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_61_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_61_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 61
+; PWR5-NEXT: subfic 3, 3, 61
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 61
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_61_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 61
+; PWR6-NEXT: subfic 3, 3, 61
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 61
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_61_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 61
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 61
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_61_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI220_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI220_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_61_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI220_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI220_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 61, i64 61>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_62_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_62_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 62
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_62_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 62
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_62_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 62
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 62
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_62_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI221_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI221_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_62_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI221_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI221_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 62, i64 62>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ugt_62_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ugt_62_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: li 5, 62
+; PWR5-NEXT: subfic 3, 3, 62
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 5, 5
+; PWR5-NEXT: subfic 4, 4, 62
+; PWR5-NEXT: subfe 4, 5, 5
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ugt_62_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: li 5, 62
+; PWR6-NEXT: subfic 3, 3, 62
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 5, 5
+; PWR6-NEXT: subfic 4, 4, 62
+; PWR6-NEXT: subfe 4, 5, 5
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ugt_62_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 62
+; PWR7-NEXT: iselgt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 62
+; PWR7-NEXT: iselgt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ugt_62_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI222_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI222_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 2, 3
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ugt_62_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI222_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI222_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 2, 3
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ugt <2 x i64> %2, <i64 62, i64 62>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+define <2 x i64> @ult_63_v2i64(<2 x i64> %0) {
+; PWR5-LABEL: ult_63_v2i64:
+; PWR5: # %bb.0:
+; PWR5-NEXT: lis 5, 21845
+; PWR5-NEXT: lis 6, 13107
+; PWR5-NEXT: ori 5, 5, 21845
+; PWR5-NEXT: rotldi 8, 4, 63
+; PWR5-NEXT: rotldi 9, 3, 63
+; PWR5-NEXT: rldimi 5, 5, 32, 0
+; PWR5-NEXT: and 8, 8, 5
+; PWR5-NEXT: and 5, 9, 5
+; PWR5-NEXT: ori 6, 6, 13107
+; PWR5-NEXT: sub 3, 3, 5
+; PWR5-NEXT: rldimi 6, 6, 32, 0
+; PWR5-NEXT: sub 4, 4, 8
+; PWR5-NEXT: and 8, 3, 6
+; PWR5-NEXT: rotldi 3, 3, 62
+; PWR5-NEXT: and 3, 3, 6
+; PWR5-NEXT: lis 7, 3855
+; PWR5-NEXT: and 5, 4, 6
+; PWR5-NEXT: rotldi 4, 4, 62
+; PWR5-NEXT: add 3, 8, 3
+; PWR5-NEXT: lis 9, 257
+; PWR5-NEXT: ori 7, 7, 3855
+; PWR5-NEXT: and 4, 4, 6
+; PWR5-NEXT: rldicl 6, 3, 60, 4
+; PWR5-NEXT: ori 9, 9, 257
+; PWR5-NEXT: rldimi 7, 7, 32, 0
+; PWR5-NEXT: add 4, 5, 4
+; PWR5-NEXT: add 3, 3, 6
+; PWR5-NEXT: rldimi 9, 9, 32, 0
+; PWR5-NEXT: rldicl 5, 4, 60, 4
+; PWR5-NEXT: and 3, 3, 7
+; PWR5-NEXT: add 4, 4, 5
+; PWR5-NEXT: mulld 3, 3, 9
+; PWR5-NEXT: and 4, 4, 7
+; PWR5-NEXT: rldicl 3, 3, 8, 56
+; PWR5-NEXT: li 5, 63
+; PWR5-NEXT: mulld 4, 4, 9
+; PWR5-NEXT: subc 6, 3, 5
+; PWR5-NEXT: rldicl 4, 4, 8, 56
+; PWR5-NEXT: subfe 3, 3, 3
+; PWR5-NEXT: subc 5, 4, 5
+; PWR5-NEXT: subfe 4, 4, 4
+; PWR5-NEXT: blr
+;
+; PWR6-LABEL: ult_63_v2i64:
+; PWR6: # %bb.0:
+; PWR6-NEXT: lis 5, 21845
+; PWR6-NEXT: lis 6, 13107
+; PWR6-NEXT: ori 5, 5, 21845
+; PWR6-NEXT: rotldi 8, 4, 63
+; PWR6-NEXT: rotldi 9, 3, 63
+; PWR6-NEXT: rldimi 5, 5, 32, 0
+; PWR6-NEXT: and 8, 8, 5
+; PWR6-NEXT: and 5, 9, 5
+; PWR6-NEXT: ori 6, 6, 13107
+; PWR6-NEXT: sub 3, 3, 5
+; PWR6-NEXT: rldimi 6, 6, 32, 0
+; PWR6-NEXT: sub 4, 4, 8
+; PWR6-NEXT: and 8, 3, 6
+; PWR6-NEXT: rotldi 3, 3, 62
+; PWR6-NEXT: and 3, 3, 6
+; PWR6-NEXT: lis 7, 3855
+; PWR6-NEXT: and 5, 4, 6
+; PWR6-NEXT: rotldi 4, 4, 62
+; PWR6-NEXT: add 3, 8, 3
+; PWR6-NEXT: lis 9, 257
+; PWR6-NEXT: ori 7, 7, 3855
+; PWR6-NEXT: and 4, 4, 6
+; PWR6-NEXT: rldicl 6, 3, 60, 4
+; PWR6-NEXT: ori 9, 9, 257
+; PWR6-NEXT: rldimi 7, 7, 32, 0
+; PWR6-NEXT: add 4, 5, 4
+; PWR6-NEXT: add 3, 3, 6
+; PWR6-NEXT: rldimi 9, 9, 32, 0
+; PWR6-NEXT: rldicl 5, 4, 60, 4
+; PWR6-NEXT: and 3, 3, 7
+; PWR6-NEXT: add 4, 4, 5
+; PWR6-NEXT: mulld 3, 3, 9
+; PWR6-NEXT: and 4, 4, 7
+; PWR6-NEXT: rldicl 3, 3, 8, 56
+; PWR6-NEXT: li 5, 63
+; PWR6-NEXT: mulld 4, 4, 9
+; PWR6-NEXT: subc 6, 3, 5
+; PWR6-NEXT: rldicl 4, 4, 8, 56
+; PWR6-NEXT: subfe 3, 3, 3
+; PWR6-NEXT: subc 5, 4, 5
+; PWR6-NEXT: subfe 4, 4, 4
+; PWR6-NEXT: blr
+;
+; PWR7-LABEL: ult_63_v2i64:
+; PWR7: # %bb.0:
+; PWR7-NEXT: addi 3, 1, -32
+; PWR7-NEXT: li 5, 0
+; PWR7-NEXT: li 6, -1
+; PWR7-NEXT: stxvd2x 34, 0, 3
+; PWR7-NEXT: ld 3, -24(1)
+; PWR7-NEXT: ld 4, -32(1)
+; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: cmpldi 3, 63
+; PWR7-NEXT: isellt 3, 6, 5
+; PWR7-NEXT: cmpldi 4, 63
+; PWR7-NEXT: isellt 4, 6, 5
+; PWR7-NEXT: std 3, -8(1)
+; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 4, -16(1)
+; PWR7-NEXT: lxvd2x 34, 0, 3
+; PWR7-NEXT: blr
+;
+; PWR8-LABEL: ult_63_v2i64:
+; PWR8: # %bb.0:
+; PWR8-NEXT: addis 3, 2, .LCPI223_0 at toc@ha
+; PWR8-NEXT: vpopcntd 2, 2
+; PWR8-NEXT: addi 3, 3, .LCPI223_0 at toc@l
+; PWR8-NEXT: lxvd2x 35, 0, 3
+; PWR8-NEXT: vcmpgtud 2, 3, 2
+; PWR8-NEXT: blr
+;
+; PWR9-LABEL: ult_63_v2i64:
+; PWR9: # %bb.0:
+; PWR9-NEXT: addis 3, 2, .LCPI223_0 at toc@ha
+; PWR9-NEXT: vpopcntd 2, 2
+; PWR9-NEXT: addi 3, 3, .LCPI223_0 at toc@l
+; PWR9-NEXT: lxvx 35, 0, 3
+; PWR9-NEXT: vcmpgtud 2, 3, 2
+; PWR9-NEXT: blr
+ %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
+ %3 = icmp ult <2 x i64> %2, <i64 63, i64 63>
+ %4 = sext <2 x i1> %3 to <2 x i64>
+ ret <2 x i64> %4
+}
+
+declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>)
+declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>)
+declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>)
+declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>)
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