[PATCH] D91048: [AMDGPU] Add new pseudos for indirect addressing with VGPR Indexing

[Austin Kerbow via Phabricator via llvm-commits]

kerbowa created this revision.
kerbowa added reviewers: rampitec, arsenm.
Herald added subscribers: llvm-commits, arphaman, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl.
Herald added a project: LLVM.
kerbowa requested review of this revision.
Herald added a subscriber: wdng.

It is possible for copies or spills to be inserted in the middle of indirect
addressing sequences which use VGPR indexing. Spills to accvgprs could be
effected by the indexing mode.

Add new pseudo instructions that are expanded after register allocation to avoid
the problematic spill or copy placement.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D91048

Files:
  llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.h
  llvm/lib/Target/AMDGPU/SIInstructions.td
  llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir
  llvm/test/CodeGen/AMDGPU/indirect-addressing-si-gfx9.ll
  llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
  llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D91048.303755.patch
Type: text/x-patch
Size: 89529 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20201109/8abdc087/attachment-0001.bin>