[PATCH] D90844: [TableGen][SchedModels] Fix read/write variant substitution #2

Sat Nov 7 10:38:45 PST 2020

evgeny777 added inline comments.

================
Comment at: llvm/lib/Target/ARM/ARMScheduleA57.td:180
 // May be an error in doc.
-def A57WriteALUsi : SchedWriteVariant<[
-  // lsl #2, lsl #1, or lsr #1.
----------------
dmgreen wrote:
> This is "Move, shift by immed, no setflags"  _and_  "Move, shift by immed, setflags"?
> I agree that the predicated pred should not matter, but there probably should be some difference between flag setting and not.
> 
> I think the TODO above is referring to A57WriteALUSsr? I'm not sure why A57WriteALUsr is treated the same way though. From what I can see it should be using  A57Write_1cyc_1.
> 
> Is A57ReadALUsr worth keeping around?
> Is A57ReadALUsr worth keeping around?

I don't think it is, however I decided to keep it for now for testing purposes.

>  I'm not sure why A57WriteALUsr is treated the same way though. From what I can see it should be using A57Write_1cyc_1.
Why? From opt guide:
```
ALU, shift	by register,	
unconditional                          (same as above) 2 1 M
ALU, shift by register,	
conditional                            (same as above) 2 1 I0/I1
```

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90844/new/

https://reviews.llvm.org/D90844