[PATCH] D90730: [AMDGPU] Add default 1 glc operand to rtn atomics

[Scott Linder via Phabricator via llvm-commits]

scott.linder added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:337-338
   bool isDLC() const { return isImmTy(ImmTyDLC); }
   bool isGLC() const { return isImmTy(ImmTyGLC); }
+  bool isGLC_1() const { return isImmTy(ImmTyGLC); }
   bool isSLC() const { return isImmTy(ImmTySLC); }
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Is the `_1` variant added here rather than replacing the existing one to support an old syntax, or to support disjoint classes of instructions which need different defaults/validation, or something else? I'm not sure I understand, but renaming the `_1` to something more descriptive or adding a comment might help. It also seems like the other `isX` functions are all checking for something distinct (i.e. there is `ImmTyOffset`, `ImmTyOffset0`, and `ImmTyOffset1` above), is that not needed here?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90730/new/

https://reviews.llvm.org/D90730