[PATCH] D90946: [IR] [TableGen] Cleanup pass over the IR TableGen files
Paul C. Anagnostopoulos via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 6 07:42:19 PST 2020
Paul-C-Anagnostopoulos added inline comments.
================
Comment at: llvm/include/llvm/IR/IntrinsicsAMDGPU.td:514
bits<3> Encoding = enc;
- bit DA = 0; // DA bit in MIMG encoding
+ bit DA = false; // DA bit in MIMG encoding
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tstellar wrote:
> I think fields like this that represent bit fields in the instruction should remain 1/0.
Agreed. Thanks for checking this.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D90946/new/
https://reviews.llvm.org/D90946
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