[PATCH] D90946: [IR] [TableGen] Cleanup pass over the IR TableGen files

[Tom Stellard via Phabricator via llvm-commits]

tstellar added inline comments.


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Comment at: llvm/include/llvm/IR/IntrinsicsAMDGPU.td:514
   bits<3> Encoding = enc;
-  bit DA = 0; // DA bit in MIMG encoding
+  bit DA = false; // DA bit in MIMG encoding
 
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I think fields like this that represent bit fields in the instruction should remain 1/0.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90946/new/

https://reviews.llvm.org/D90946