[PATCH] D90853: [RISCV] Add DAG nodes to represent read/write CSR

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

What's the motivation for this?



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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:397
+    hasSideEffects = 1, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1 in
+class CSR_ir_wo<bits<3> funct3, string opcodestr>
+    : RVInstI<funct3, OPC_SYSTEM, (outs), (ins csr_sysreg:$imm12, GPR:$rs1),
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CSRW_ir might be a better name (though CSRW could be confused with the pseudoinstruction), not a huge fan of _wo.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:399
+    : RVInstI<funct3, OPC_SYSTEM, (outs), (ins csr_sysreg:$imm12, GPR:$rs1),
+              opcodestr, "$imm12, $rs1">, Sched<[WriteCSR, ReadCSR]> {
+  let rd = 0;
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This one has ReadCSR but CSR_ii_wo doesn't; which is it?


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1198-1203
+def : Pat<(riscv_read_csr simm12:$csr),
+          (CSRRS simm12:$csr, X0)>;
+def : Pat<(riscv_write_csr simm12:$csr, GPR:$rs1),
+          (CSRW simm12:$csr, GPR:$rs1)>;
+def : Pat<(riscv_write_csr simm12:$csr, uimm5:$imm),
+          (CSRW simm12:$csr, uimm5:$imm)>;
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Why do we need CSR_i[ir]_wo but not CSR_i[ir]_ro? Either both are needed if you need to be able to specify scheduling for instructions that only do one of read or write, or you don't need either of them, surely?


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  https://reviews.llvm.org/D90853/new/

https://reviews.llvm.org/D90853