[PATCH] D90853: [RISCV] Add DAG nodes to represent read/write CSR
Serge Pavlov via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 5 08:03:51 PST 2020
sepavloff created this revision.
sepavloff added reviewers: asb, craig.topper, lenary, luismarques, jrtc27.
Herald added subscribers: frasercrmck, NickHung, evandro, apazos, sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya.
Herald added a project: LLVM.
sepavloff requested review of this revision.
Herald added a subscriber: MaskRay.
Two custom DAG nodes, READ_CSR and WRITE_CSR, are added. They represent
read/write operations on CSR. Corresponding instruction patters also are
added, as existing CSRRW and others always produce value.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D90853
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/lib/Target/RISCV/RISCVInstrInfo.td
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