[PATCH] D90853: [RISCV] Add DAG nodes to represent read/write CSR

[Serge Pavlov via Phabricator via llvm-commits]

sepavloff created this revision.
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Two custom DAG nodes, READ_CSR and WRITE_CSR, are added. They represent
read/write operations on CSR. Corresponding instruction patters also are
added, as existing CSRRW and others always produce value.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D90853

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfo.td

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