[llvm] 7fe7c6d - [GlobalISel] Don't use Register type for getNumOperands(). NFCI.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2020-11-05T17:12:58Z
New Revision: 7fe7c6d3be888e4c504f62e3412c7e89358dfc28

URL: https://github.com/llvm/llvm-project/commit/7fe7c6d3be888e4c504f62e3412c7e89358dfc28
DIFF: https://github.com/llvm/llvm-project/commit/7fe7c6d3be888e4c504f62e3412c7e89358dfc28.diff

LOG: [GlobalISel] Don't use Register type for getNumOperands(). NFCI.

Copy+Paste typo - we were storing getNumOperands() opcounts in a Register type instead of just an unsigned.

Added: 
    

Modified: 
    llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp b/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
index 97aae2db2706..a7204fe4e611 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
@@ -416,7 +416,7 @@ void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known,
     break;
   }
   case TargetOpcode::G_MERGE_VALUES: {
-    Register NumOps = MI.getNumOperands();
+    unsigned NumOps = MI.getNumOperands();
     unsigned OpSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
 
     for (unsigned I = 0; I != NumOps - 1; ++I) {
@@ -428,7 +428,7 @@ void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known,
     break;
   }
   case TargetOpcode::G_UNMERGE_VALUES: {
-    Register NumOps = MI.getNumOperands();
+    unsigned NumOps = MI.getNumOperands();
     Register SrcReg = MI.getOperand(NumOps - 1).getReg();
     if (MRI.getType(SrcReg).isVector())
       return; // TODO: Handle vectors.