[llvm] f38d1a9 - [ARM] Make tests less dependent on scheduling. NFC

[David Green via llvm-commits]

Author: David Green
Date: 2020-11-05T08:26:55Z
New Revision: f38d1a95e9a8b24aca0f267e3963d38dca37e00f

URL: https://github.com/llvm/llvm-project/commit/f38d1a95e9a8b24aca0f267e3963d38dca37e00f
DIFF: https://github.com/llvm/llvm-project/commit/f38d1a95e9a8b24aca0f267e3963d38dca37e00f.diff

LOG: [ARM] Make tests less dependent on scheduling. NFC

Added: 
    

Modified: 
    llvm/test/CodeGen/Thumb2/float-intrinsics-double.ll
    llvm/test/CodeGen/Thumb2/ifcvt-no-branch-predictor.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/Thumb2/float-intrinsics-double.ll b/llvm/test/CodeGen/Thumb2/float-intrinsics-double.ll
index a691fd553665..29843a51fc2a 100644
--- a/llvm/test/CodeGen/Thumb2/float-intrinsics-double.ll
+++ b/llvm/test/CodeGen/Thumb2/float-intrinsics-double.ll
@@ -109,12 +109,12 @@ declare double     @llvm.fabs.f64(double %Val)
 define double @abs_d(double %a) {
 ; CHECK-LABEL: abs_d:
 ; NONE: bic r1, r1, #-2147483648
-; SP: vldr d1, .LCPI{{.*}}
-; SP: vmov r0, r1, d0
-; SP: vmov r2, r3, d1
-; SP: lsrs r2, r3, #31
-; SP: bfi r1, r2, #31, #1
-; SP: vmov d0, r0, r1
+; SP: vldr [[D1:d[0-9]+]], .LCPI{{.*}}
+; SP-DAG: vmov [[R2:r[0-9]+]], [[R3:r[0-9]+]], [[D1]]
+; SP-DAG: vmov [[R0:r[0-9]+]], [[R1:r[0-9]+]], [[D0:d[0-9]+]]
+; SP: lsrs [[R4:r[0-9]+]], [[R3]], #31
+; SP: bfi [[R5:r[0-9]+]], [[R4]], #31, #1
+; SP: vmov [[D0]], [[R0]], [[R5]]
 ; DP: vabs.f64 d0, d0
   %1 = call double @llvm.fabs.f64(double %a)
   ret double %1
@@ -123,10 +123,10 @@ define double @abs_d(double %a) {
 declare double     @llvm.copysign.f64(double  %Mag, double  %Sgn)
 define double @copysign_d(double %a, double %b) {
 ; CHECK-LABEL: copysign_d:
-; SOFT: lsrs [[REG:r[0-9]+]], r3, #31
-; SOFT: bfi r1, [[REG]], #31, #1
-; VFP: lsrs [[REG:r[0-9]+]], r3, #31
-; VFP: bfi r1, [[REG]], #31, #1
+; SOFT: lsrs [[REG:r[0-9]+]], {{r[0-9]+}}, #31
+; SOFT: bfi {{r[0-9]+}}, [[REG]], #31, #1
+; VFP: lsrs [[REG:r[0-9]+]], {{r[0-9]+}}, #31
+; VFP: bfi {{r[0-9]+}}, [[REG]], #31, #1
 ; NEON:         vmov.i32 d16, #0x80000000
 ; NEON-NEXT:    vshl.i64 d16, d16, #32
 ; NEON-NEXT:    vbit d0, d1, d16

diff  --git a/llvm/test/CodeGen/Thumb2/ifcvt-no-branch-predictor.ll b/llvm/test/CodeGen/Thumb2/ifcvt-no-branch-predictor.ll
index b6b4805b97d9..8d338dad9bc7 100644
--- a/llvm/test/CodeGen/Thumb2/ifcvt-no-branch-predictor.ll
+++ b/llvm/test/CodeGen/Thumb2/ifcvt-no-branch-predictor.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=thumbv7m -mcpu=cortex-m7 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BP
+; RUN: llc < %s -mtriple=thumbv7m -mattr=-no-branch-predictor | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BP
 ; RUN: llc < %s -mtriple=thumbv7m -mcpu=cortex-m3 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOBP
 
 declare void @otherfn()
@@ -64,6 +64,7 @@ if.then:
   store i32 1, i32* %p, align 4
   store i32 2, i32* %q, align 4
   store i32 3, i32* %r, align 4
+  store i32 4, i32* %p, align 4
   br label %if.end
 
 if.end: