[PATCH] D90829: [GlobalISel][TableGen] fix seg fault for zero instruction

[Gabriel Hjort Åkerlund via Phabricator via llvm-commits]

ehjogab created this revision.
ehjogab added reviewers: dsanders, arsenm, qcolombet, ab, bjope, rovka.
Herald added a project: LLVM.
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Herald added a subscriber: wdng.

Tablegen seg faulted when parsing a Pat where the destination part has
no output (zero instruction), due to a register class lookup using
nullptr.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D90829

Files:
  llvm/test/TableGen/GlobalISelEmitter-zero-instr.td
  llvm/utils/TableGen/GlobalISelEmitter.cpp


Index: llvm/utils/TableGen/GlobalISelEmitter.cpp
===================================================================
--- llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -5086,9 +5086,9 @@
 
   if (Dst->isLeaf()) {
     Record *RCDef = getInitValueAsRegClass(Dst->getLeafValue());
-
-    const CodeGenRegisterClass &RC = Target.getRegisterClass(RCDef);
     if (RCDef) {
+      const CodeGenRegisterClass &RC = Target.getRegisterClass(RCDef);
+
       // We need to replace the def and all its uses with the specified
       // operand. However, we must also insert COPY's wherever needed.
       // For now, emit a copy and let the register allocator clean up.
Index: llvm/test/TableGen/GlobalISelEmitter-zero-instr.td
===================================================================
--- /dev/null
+++ llvm/test/TableGen/GlobalISelEmitter-zero-instr.td
@@ -0,0 +1,8 @@
+// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
+
+include "llvm/Target/Target.td"
+include "GlobalISelEmitterCommon.td"
+
+// CHECK: return MatchTable
+def : Pat<(zext (i16 (trunc i32:$src))),
+          (i32 $src)>;


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