[PATCH] D90738: [RISCV] Support Zfh half-precision floating-point extension.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2836
       }
-      return std::make_pair(FReg, &RISCV::FPR32RegClass);
+      unsigned HReg = RISCV::F0_H + RegNo;
+      return std::make_pair(HReg, &RISCV::FPR16RegClass);
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I don't think this is needed at all. Won't StdExtF be enabled when Zfh is enabled?


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1521
 };
+static const MCPhysReg ArgFPR16s[] = {RISCV::F10_H, RISCV::F11_H, RISCV::F12_H,
+                                      RISCV::F13_H, RISCV::F14_H, RISCV::F15_H,
----------------
HsiangKai wrote:
> craig.topper wrote:
> > Can we line break this the same way as FPR32s/FPR64s for consisency?
> It is arranged by clang-format. What should I follow? I also prefer to keep the consistency.
I find the FPR32s/FPR64s easier to read so I think we can ignore clang-format here.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90738/new/

https://reviews.llvm.org/D90738