[PATCH] D90738: [RISCV] Support Zfh half-precision floating-point extension.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1521
 };
+static const MCPhysReg ArgFPR16s[] = {RISCV::F10_H, RISCV::F11_H, RISCV::F12_H,
+                                      RISCV::F13_H, RISCV::F14_H, RISCV::F15_H,
----------------
craig.topper wrote:
> Can we line break this the same way as FPR32s/FPR64s for consisency?
It is arranged by clang-format. What should I follow? I also prefer to keep the consistency.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1705
   if (ValVT == MVT::f32 && !UseGPRForF32)
     Reg = State.AllocateReg(ArgFPR32s, ArgFPR64s);
   else if (ValVT == MVT::f64 && !UseGPRForF64)
----------------
craig.topper wrote:
> craig.topper wrote:
> > The second argument is shadow regs. Do we need a way to shaddow ArgFPR16s here.
> Thinking more about this, since the fp registers are sub/super registers, we may not need shadows registers here at all.
> 
> I've posted D90801 to remove the shadow arguments here.
I agree with you. Thanks.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90738/new/

https://reviews.llvm.org/D90738