[PATCH] D90735: [RISCV] Correct the operand order for fshl/fshr to fsl/fsr instructions.

[Craig Topper via Phabricator via llvm-commits]

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fsl/fsr take their shift amount in $rs2 or an immediate. The
sources are $rs1 and $rs3.

fshl/fshr ISD opcodes both concatenate operand 0 in the high bits and
operand 1 in the lower bits. fshl returns the high bits after
shifting and fshr returns the low bits. So a shift amount of 0
returns operand 0 for fshl and operand 1 for fshr.

fsl/fsr concatenate their operands in different orders such that
$rs1 will be returned for a shift amount of 0. So $rs1 needs to
come from operand 0 of fshl and operand 1 of fshr.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D90735

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv32Zbb.ll
  llvm/test/CodeGen/RISCV/rv32Zbbp.ll
  llvm/test/CodeGen/RISCV/rv32Zbt.ll
  llvm/test/CodeGen/RISCV/rv64Zbt.ll

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