[PATCH] D90678: [AVR] Optimize 8-bit int shift

[Ben Shi via Phabricator via llvm-commits]

benshi001 added a comment.

It is hard to use SelectionDAG instead of Pseudo instructions for this optimization.

Since for LSL7, the instr serial is

  ROR Rx 
  CLR Rx
  ROR Rx

There is no dependancy between ROR and CLR, so DAG can not be created properly.

This patch is a supplement to https://reviews.llvm.org/D89047


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90678/new/

https://reviews.llvm.org/D90678