[PATCH] D89047: [AVR] Optimize 8-bit logic left/right shifts

[Ben Shi via Phabricator via llvm-commits]

benshi001 added a comment.

I have uploaded a new revision with more tests.

Now llvm-avr generates the same asm for logic left/right shifts when ShiftAmount = 1,2,3,4,5,6, except for 7.

This is shown in the test llvm/test/CodeGen/AVR/shift.ll.

Shall we commit this first? Then I will go on with the specific case ShiftAmount=7 in another patch.


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  https://reviews.llvm.org/D89047/new/

https://reviews.llvm.org/D89047