[llvm] a76cd10 - [RISCV] Use 'unsigned' instead of Register in getRegForInlineAsmConstraint. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2020-11-01T10:16:52-08:00
New Revision: a76cd10fcda53160dd213157740b2efb31e73e8d

URL: https://github.com/llvm/llvm-project/commit/a76cd10fcda53160dd213157740b2efb31e73e8d
DIFF: https://github.com/llvm/llvm-project/commit/a76cd10fcda53160dd213157740b2efb31e73e8d.diff

LOG: [RISCV] Use 'unsigned' instead of Register in getRegForInlineAsmConstraint. NFC

The return value of this interface still uses an 'unsigned' on all
targets. So we convert Register back to unsigned at the end.

I'm hoping this will prevent the issue that caused the revert of
D90322.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d2606f4e8b7c..b16743a688ad 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -2674,7 +2674,7 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
   // official names. However, other frontends like `rustc` do not. This allows
   // users of these frontends to use the ABI names for registers in LLVM-style
   // register constraints.
-  Register XRegFromAlias = StringSwitch<Register>(Constraint.lower())
+  unsigned XRegFromAlias = StringSwitch<unsigned>(Constraint.lower())
                                .Case("{zero}", RISCV::X0)
                                .Case("{ra}", RISCV::X1)
                                .Case("{sp}", RISCV::X2)
@@ -2719,8 +2719,8 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
   // The second case is the ABI name of the register, so that frontends can also
   // use the ABI names in register constraint lists.
   if (Subtarget.hasStdExtF() || Subtarget.hasStdExtD()) {
-    std::pair<Register, Register> FReg =
-        StringSwitch<std::pair<Register, Register>>(Constraint.lower())
+    std::pair<unsigned, unsigned> FReg =
+        StringSwitch<std::pair<unsigned, unsigned>>(Constraint.lower())
             .Cases("{f0}", "{ft0}", {RISCV::F0_F, RISCV::F0_D})
             .Cases("{f1}", "{ft1}", {RISCV::F1_F, RISCV::F1_D})
             .Cases("{f2}", "{ft2}", {RISCV::F2_F, RISCV::F2_D})