[PATCH] D90247: [AArch64] Add legalizations for VECREDUCE_SEQ_FADD

[Nikita Popov via Phabricator via llvm-commits]

nikic added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h:713
   SDValue SoftPromoteHalfRes_VECREDUCE(SDNode *N);
+  SDValue SoftPromoteHalfRes_VECREDUCE_SEQ(SDNode *N);
 
----------------
Looks like there is no definition for this method. There's probably no way to test it (requires X86), but I'd suggest to still include it, as the implementation is the same as the other soft float legalization. I'd also be fine with not having it, in which case this declaration should be dropped as well.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:826
+    break;
+  }
+
----------------
As this is a recurring pattern, I have extracted an `ISD::getVecReduceBaseOpcode()` function that does this. Please add VECREDUCE_SEQ_FADD there and then use it here and in expansion.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:4909
+    break;
+  }
+
----------------
Again, this is a recurring pattern, so I have extracted a `SelectionDAG::getNeutralElement()` API for this. The invocation should be:

```
SDValue NeutralElem = DAG.getNeutralElement(
    ISD::getVecReduceBaseOpcode(N->getOpcode()), dl, ElemVT, Flags);
```


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90247/new/

https://reviews.llvm.org/D90247