[PATCH] D90176: [AArch64] Improve lowering of insert_vector_elt with 0.0 consts.

[Florian Hahn via Phabricator via llvm-commits]

fhahn updated this revision to Diff 301401.
fhahn added a comment.



In D90176#2359750 <https://reviews.llvm.org/D90176#2359750>, @efriedma wrote:

>> but for some reason the matching does not work for f16
>
> I think isFPImmLegal is false, so we're forcing a constant pool.  I think you can make the testcase work with +fullfp16?

Yeah, that was the issue. Adding +fullfp16 solved the issue. Updated the tests. It's probably not worth trying to improve f16 codegen without +fullfp16.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90176/new/

https://reviews.llvm.org/D90176

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll
  llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization.ll

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