[PATCH] D88060: [GISel]: Few InsertVecElt combines
Aditya Nandakumar via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 28 12:29:52 PDT 2020
aditya_nandakumar closed this revision.
aditya_nandakumar added a comment.
rGbed839404784 <https://reviews.llvm.org/rGbed83940478449b7ee08d43e5b74995912bf8206>
================
Comment at: llvm/include/llvm/Target/GlobalISel/Combine.td:508
+def regs_small_vec : GIDefMatchData<"SmallVector<Register, 4>">;
+def combine_insert_vec_elts_build_vector : GICombineRule<
----------------
foad wrote:
> Nit: since you have given this a generic name, there are probably other places in this file that could make use of it instead of defining their own matchdata.
I'll clean them all up in a follow up NFC commit.
================
Comment at: llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp:2479
+ Register UndefReg;
+ auto GetUndef = [&]() {
+ if (UndefReg.isValid())
----------------
foad wrote:
> Nit: could inline this into its only caller.
This attempts to just cache UNDEFs without relying on CSE mechanism.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D88060/new/
https://reviews.llvm.org/D88060
More information about the llvm-commits
mailing list