[PATCH] D90176: [AArch64] Improve lowering of insert_vector_elt with 0.0 consts.

[Florian Hahn via Phabricator via llvm-commits]

fhahn updated this revision to Diff 301225.
fhahn added a comment.



In D90176#2357487 <https://reviews.llvm.org/D90176#2357487>, @efriedma wrote:

> In D90176#2357415 <https://reviews.llvm.org/D90176#2357415>, @fhahn wrote:
>
>> Thanks! I think I was running into some ambiguity with the patterns, not sure exactly what was going on. Would you prefer the tablegen version?
>
> I'm a little worried this version will make other combines more complicated; I'd prefer the TableGen version if it isn't too hard.

Thanks, I figured out what was going wrong with the tablegen version initially. The tablegen patterns now work for f32 and f64, but for some reason the matching does not work for f16.

Could this be related to fpimm0 not matching 0.0 for f16? It prints  ConstantFP:f16<APFloat(0)> instead of  ConstantFP:f32<0.00000> for f32 constants.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90176/new/

https://reviews.llvm.org/D90176

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll
  llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization.ll

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