[PATCH] D89382: [SVE][CodeGen] Lower scalable integer vector reductions

[Kerry McLaughlin via Phabricator via llvm-commits]

kmclaughlin added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll:145-152
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    umov w10, v0.h[1]
+; CHECK-NEXT:    umov w11, v0.h[0]
+; CHECK-NEXT:    umov w9, v0.h[2]
+; CHECK-NEXT:    orr w10, w11, w10
+; CHECK-NEXT:    umov w8, v0.h[3]
+; CHECK-NEXT:    orr w9, w10, w9
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paulwalker-arm wrote:
> Presumably this is down to the canonicalisation?  I'm not sure there's any immediate performance concerns here, and I stand behind canonicalisation being the correct solution.  I guess we can see if anybody disagrees with this.
> 
> The worst that can happen is more custom lowering for NEON is required but because the existing lowering doesn't do anything special for OR, and MIN/MAX operations on i1 is weird anyways, I'd rather not do that in this patch unless we really have to.
It is, I needed to change this test after I moved the transformation of vecreduce_umax to getNode()


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  https://reviews.llvm.org/D89382/new/

https://reviews.llvm.org/D89382