[llvm] 99b2756 - [ARM][SchedModels] Get rid of IsLdrAm2ScaledPred
Evgeny Leviant via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 26 02:02:11 PDT 2020
Author: Evgeny Leviant
Date: 2020-10-26T12:01:39+03:00
New Revision: 99b2756517f23252d1bd60f2a15c5799df054ef3
URL: https://github.com/llvm/llvm-project/commit/99b2756517f23252d1bd60f2a15c5799df054ef3
DIFF: https://github.com/llvm/llvm-project/commit/99b2756517f23252d1bd60f2a15c5799df054ef3.diff
LOG: [ARM][SchedModels] Get rid of IsLdrAm2ScaledPred
Differential revision: https://reviews.llvm.org/D90024
Added:
Modified:
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/lib/Target/ARM/ARMBaseInstrInfo.h
llvm/lib/Target/ARM/ARMScheduleA57.td
llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 76e1ecd71914..0cdc2eb1d2b0 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -634,13 +634,6 @@ bool ARMBaseInstrInfo::isLdstScaledRegNotPlusLsl2(const MachineInstr &MI,
return !SimpleScaled;
}
-// Load, scaled register offset
-bool ARMBaseInstrInfo::isAm2ScaledReg(const MachineInstr &MI,
- unsigned Op) const {
- unsigned OffImm = MI.getOperand(Op + 2).getImm();
- return ARM_AM::getAM2ShiftOpc(OffImm) != ARM_AM::no_shift;
-}
-
static bool isEligibleForITBlock(const MachineInstr *MI) {
switch (MI->getOpcode()) {
default: return true;
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index ad66c86c4d07..04aa33f536bd 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -181,8 +181,6 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
// Load, scaled register offset, not plus LSL2
bool isLdstScaledRegNotPlusLsl2(const MachineInstr &MI, unsigned Op) const;
- // Scaled register offset in address mode 2
- bool isAm2ScaledReg(const MachineInstr &MI, unsigned Op) const;
/// GetInstSize - Returns the size of the specified MachineInstr.
///
diff --git a/llvm/lib/Target/ARM/ARMScheduleA57.td b/llvm/lib/Target/ARM/ARMScheduleA57.td
index d7a1ae58ee05..f0bb5c7a650c 100644
--- a/llvm/lib/Target/ARM/ARMScheduleA57.td
+++ b/llvm/lib/Target/ARM/ARMScheduleA57.td
@@ -55,10 +55,6 @@ def IsLdstsoMinusRegPredX0 : MCSchedPredicate<CheckAM2OpSub<2>>;
def IsLdstsoMinusRegPred : MCSchedPredicate<CheckAM2OpSub<3>>;
def IsLdstsoMinusRegPredX2 : MCSchedPredicate<CheckAM2OpSub<4>>;
-// Load, scaled register offset
-def IsLdrAm2ScaledPred :
- SchedPredicate<[{TII->isAm2ScaledReg(*MI, 1)}]>;
-
// LDM, base reg in list
def IsLDMBaseRegInListPred : MCSchedPredicate<IsLDMBaseRegInList>;
@@ -464,11 +460,11 @@ def : InstRW<[A57Write_4cyc_1L_1I, A57WrBackTwo], (instregex "LDR_POST_REG",
"LDRB_POST_REG", "LDR(B?)T_POST$")>;
def A57WriteLdrTRegPost : SchedWriteVariant<[
- SchedVar<IsLdrAm2ScaledPred, [A57Write_4cyc_1I_1L_1M]>,
+ SchedVar<IsLdstsoScaledPredX2, [A57Write_4cyc_1I_1L_1M]>,
SchedVar<NoSchedPred, [A57Write_4cyc_1L_1I]>
]>;
def A57WriteLdrTRegPostWrBack : SchedWriteVariant<[
- SchedVar<IsLdrAm2ScaledPred, [A57WrBackThree]>,
+ SchedVar<IsLdstsoScaledPredX2, [A57WrBackThree]>,
SchedVar<NoSchedPred, [A57WrBackTwo]>
]>;
// 4(3) "I0/I1,L,M" for scaled register, otherwise 4(2) "I0/I1,L"
diff --git a/llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s b/llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
index aa614f5333a9..55d5ad4aebde 100644
--- a/llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
+++ b/llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
@@ -199,7 +199,7 @@
# CHECK-NEXT: 2 4 1.00 * ldrbt r3, [r1], #4
# CHECK-NEXT: 2 4 1.00 * ldrbt r2, [r8], #-8
# CHECK-NEXT: 2 4 1.00 * ldrbt r8, [r7], r6
-# CHECK-NEXT: 2 4 1.00 * ldrbt r1, [r2], -r6, lsl #12
+# CHECK-NEXT: 3 4 1.00 * ldrbt r1, [r2], -r6, lsl #12
# CHECK-NEXT: 2 4 2.00 * ldrd r0, r1, [r5]
# CHECK-NEXT: 2 4 2.00 * ldrd r0, r1, [r5, r2]
# CHECK-NEXT: 4 5 2.00 * ldrd r0, r1, [r5, -r2]
@@ -335,7 +335,7 @@
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6]
-# CHECK-NEXT: - 69.00 69.00 167.00 9.00 57.00 - -
+# CHECK-NEXT: - 69.00 69.00 167.00 10.00 57.00 - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6] Instructions:
@@ -371,7 +371,7 @@
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrbt r3, [r1], #4
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrbt r2, [r8], #-8
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrbt r8, [r7], r6
-# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrbt r1, [r2], -r6, lsl #12
+# CHECK-NEXT: - 0.50 0.50 1.00 1.00 - - - ldrbt r1, [r2], -r6, lsl #12
# CHECK-NEXT: - - - 2.00 - - - - ldrd r0, r1, [r5]
# CHECK-NEXT: - - - 2.00 - - - - ldrd r0, r1, [r5, r2]
# CHECK-NEXT: - 1.00 1.00 2.00 - - - - ldrd r0, r1, [r5, -r2]
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