[PATCH] D90029: [ARM][SchedModels] Convert IsLdstsoMinusRegPred to MCSchedPredicate

[Eugene Leviant via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGa4fc18e6410f: [ARM][SchedModels] Convert IsLdstsoMinusRegPred to MCSchedPredicate (authored by evgeny777).

Changed prior to commit:
  https://reviews.llvm.org/D90029?vs=300267&id=300597#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90029/new/

https://reviews.llvm.org/D90029

Files:
  llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.h
  llvm/lib/Target/ARM/ARMSchedule.td
  llvm/lib/Target/ARM/ARMScheduleA57.td
  llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D90029.300597.patch
Type: text/x-patch
Size: 13388 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20201026/a25b31bb/attachment.bin>