[PATCH] D90024: [ARM][SchedModels] Get rid of IsLdrAm2ScaledPred

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

> (paranoia level).
> Are we sure that the lowering of MachineInstr to MCInst is preserving the operand sequence? Can it be that the immediate is at position 4 for the MCInst only?
> I have no idea how an ldrbt looks like as a MachineInstr. The original check should have triggered an assertion too for MachineInstr then...

I was not aware that was a thing that could happen!

I'm unsure if anything would ever generate an ldrbt with negative postinc reg and shift from codegen, so it might be difficult to test. And may never have been tested in the past.


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  https://reviews.llvm.org/D90024/new/

https://reviews.llvm.org/D90024