[PATCH] D90024: [ARM][SchedModels] Get rid of IsLdrAm2ScaledPred

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb added a comment.

In D90024#2350392 <https://reviews.llvm.org/D90024#2350392>, @evgeny777 wrote:

>> Should it always have been checking operand 4 then? I think that makes sense
>
> IMO, it was incorrectly checking for operand 3. I've got an assertion when switched to MC pred

(paranoia level).
Are we sure that the lowering of MachineInstr to MCInst is preserving the operand sequence? Can it be that the immediate is at position 4 for the MCInst only?
I have no idea how an ldrbt looks like as a MachineInstr. The original check should have triggered an assertion too for MachineInstr then...


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https://reviews.llvm.org/D90024